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non clcok cells on clock path

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qual_ti

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Hi,

I am seeing some non clock cell in clock path and some clock cells in data path.

these paths causing timing violations .Is these paths need to be fixed ?

If we have such non clock cells in clock path, does it cause any violations ?

Can we tape out such data base after fixing those violations with above condition ?

Please give needed data in this regard .


Regards
qual_ti
 

Hi qual_ti!

I am wondering where ur physical and circuit came from?

I've achieved aproject that some non clock cell in the clock path, but It is a very slow project (clk period = 9ms), and there's no timing violation during STA.

Normally, we can not add non clock cell into the clk path during CTS, course backend tools do not allow to do so.
Non clock cells can not met the clkbufs' default setting, such as tinming, drive, load attributes.
 

Hi When you build the Clock tree you need to specify the cells or buffers to be used. Usually these CT cells are hidden and you need to unhide them for the tool to use. And no, you should not use these cells in the clock path. It will affect your clock tree robustness
 

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