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    Error: Port "i1" does not exist in primitive "nand2" of instance "g2"

    i have some problem using quartus ii 11

    my code is:

    LIBRARY ieee ;
    USE ieee.std_logic_1164.all ;
    USE ieee.std_logic_signed.all;

    entity bit_comparator2 is
    port(a, b, gt, eq, lt :in bit; agtb, aeqb, altb :out bit);
    end bit_comparator2;
    --


    architecture gate_level of bit_comparator2 is
    component inv port (i1:in bit; o1:out bit); end component;
    component nand2 port(i1,i2:in bit; o1:out bit); end component;
    component nand3 port(i1,i2,i3:in bit; o1:out bit); end component;


    signal im1,im2,im3,im4,im5,im6,im7,im8,im9,im10:bit;
    begin
    --agtb output
    g0 : inv port map(a,im1);
    g1 : inv port map(b,im2);
    g2 : nand2 port map(a,im2,im3);
    g3 : nand2 port map(a,gt,im4);
    g4 : nand2 port map(im2,gt,im5);
    g5 : nand3 port map(im3,im4,im5,agtb);
    --aeqb ouyput
    g6 : nand3 port map(im1,im2,eq,im6);
    g7 : nand3 port map(a,b,eq,im7);
    g8 : nand2 port map(im6,im7,aeqb);
    --altb output
    g9 : nand2 port map(im1,b,im8);
    g10: nand2 port map(im1,lt,im9);
    g11: nand2 port map(b,lt,im10);
    g12: nand3 port map(im8,im9,im10,altb);
    end gate_level;






    -------------------


    ----
    LIBRARY ieee ;
    USE ieee.std_logic_1164.all ;
    USE ieee.std_logic_signed.all;
    entity inv is
    port(i1:in bit; o1:out bit);
    end inv;

    architecture single_delay of inv is
    begin
    o1 <= not i1 ;
    end single_delay;


    ----------
    LIBRARY ieee ;
    USE ieee.std_logic_1164.all ;
    USE ieee.std_logic_signed.all;
    entity nand2 is
    port(i1,i2:in bit; o1:out bit);
    end nand2;
    --
    architecture single_delay1 of nand2 is
    begin
    o1 <= i1 nand i2 ;
    end single_delay1;





    LIBRARY ieee ;
    USE ieee.std_logic_1164.all ;
    USE ieee.std_logic_signed.all;
    entity nand3 is
    port(i1,i2,i3:in bit; o1:out bit);
    end nand3;
    --
    architecture single_delay2 of nand3 is
    begin
    o1 <= not(i1 and i2 and i3) ;
    end single_delay2;
    When I compile it have a problem with this notice:
    Error: Port "i1" does not exist in primitive "nand2" of instance "g2"
    Error: Port "i2" does not exist in primitive "nand2" of instance "g2"
    Error: Port "o1" does not exist in primitive "nand2" of instance "g2"
    Error: Can't elaborate top-level user hierarchy
    Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 8 warnings

    can any body help?

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  2. #2
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    Re: Error: Port "i1" does not exist in primitive "nand2" of instance "g2"

    I think nand2 and nand3 exist as basic altera primatives, and its probably trying to use those. I wouldnt define your own. Change the name of nand2 and nand3.

    Or you havent included the code for nand2 in your project.


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  3. #3
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    alizadeharand's Avatar
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    Re: Error: Port "i1" does not exist in primitive "nand2" of instance "g2"

    thank you

    that was helpfull



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