+ Post New Thread
Results 1 to 2 of 2
  1. #1
    Newbie level 6
    Points: 1,019, Level: 7

    Join Date
    May 2010
    Location
    Malaysia
    Posts
    11
    Helped
    0 / 0
    Points
    1,019
    Level
    7

    Is this following code can be converted to Verilog HDL code?

    Hi all,

    I am trying to convert the following code into verilog... First i want to sure that the following MATLAB Code can be converted into Verilog HDL


    %%%%%%%%%%%%
    clc
    clear all

    % Load data -----------------------------------
    [fname, path] = uigetfile('*.txt','Open data file');
    patient_data = fname(1:end-4);
    p = -textread([path fname]);

    N = length(p);
    sr = 100; % Sampling rate
    t = (1:N)'/sr;
    % -----------------------------------------------

    % Finding all beats of 2nd derivative -------
    f = gradient(gradient(p));
    dt = .5; % Minimal pulse period
    d = 10*median(abs(f)); % Amplitude threshold
    n = find(f(1:end-1)<d & f(2:end)>d);
    n = n(diff(n)/sr>dt);

    % Finding local minimums and maximums
    for j = 1: length(n)-1
    [Amax(j),ind] = max(f(n(j):n(j+1)));
    imax(j) = n(j)-1+ ind;
    [Amin(j),ind] = min(f(n(j):n(j+1)));
    imin(j) = n(j)-1+ ind;
    end
    % -----------------------------------------------

    % The median b/a parameter value is here
    b_a = -median(Amin./Amax);


    %%%%%%%%%%%%%%%

    The deadline is very near so please help me to figure our whether it can be converted into Verilog . If possible how? If no then why?

    Thanx

    •   AltAdvertisment

        
       

  2. #2
    Super Moderator
    Points: 249,762, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    43,484
    Helped
    13214 / 13214
    Points
    249,762
    Level
    100

    Re: Is this following code can be converted to Verilog HDL code?

    - What do you exactly mean with converted into Verilog HDL? Simulation or synthesize a hardware?
    - Are you talking about using a Matlab code generator or designing generic HDL code?

    If you target to generic Verilog, you'll mainly have to define code to calculate derivative, median etc. In Matlab these operators apply to full data structures. You need to perform the respective calculations per data element, most likely in a sequence, one element per clock cycle.

    In case of Verilog for synthesis, suitable numeric formats must be selected, the file operation has to be replaced by an interface to a data source.


    1 members found this post helpful.

--[[ ]]--