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  1. #1
    Junior Member level 2
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    Please help using sdf file in Synopsys and ModelSim?

    Hi every one
    I am calculating Area, power and timing in ASIC using Synopsys Design Compiler and ModelSim. After Anlyzing and elaborating the design then applying constraint and Compiling, I saved the sdf file (using Design Compiler) as follow:

    write_sdf ./SYNOPS/SOURCE/test_defult.sdf

    when I use ModelSim Command:

    vsim -sdfmax /kkk_tb/uut=./SYNOPS/SOURCE/test_default.sdf work.kkk_tb

    I got the following Errors:

    ** Error: (vsim-SDF-3250) ./SYNOPS/SOURCE/test_default.sdf(60): Failed to find INSTANCE '\output_reg[0] '
    .
    .
    .

    ** Error: (vsim-SDF-3250) ./SYNOPS/SOURCE/test_default.sdf(57): Failed to find INSTANCE '\x0_reg[0] '.


    Please any suggestion ??

    thanks

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  2. #2
    Junior Member level 2
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    Re: Please help using sdf file in Synopsys and ModelSim?

    Hi
    I could solve the problem by deleting the following line from my code:

    change_names -rule verilog -hierarchy

    thanks



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  3. #3
    Member level 3
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    Re: Please help using sdf file in Synopsys and ModelSim?

    I dont think it is actually the answer.

    Make sure there is no command between write and write_sdf in your synthesis script



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  4. #4
    Advanced Member level 3
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    Re: Please help using sdf file in Synopsys and ModelSim?

    yes, please check synthesis script before you do run!



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