[SOLVED] Driving two PCB Traces

Hi All,

One of my I/O output pin is to be connected to two input pins (on different ICs).
Rather than routing daisy-chained from

Driver --> Receiver1 --> Receiver2 -> Termination

I would like to route two separate traces from driver

|----------> Receiver1 --> Termination
Driver
|----------> Receiver2 --> Termination

How should the traces be designed?
Do I have to double the characteristic impedance of the traces?

Thanks,
Newbie101

Do I have to double the characteristic impedance of the traces?

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This may be difficult with resonable trace parameters. You would rather reduce the source impedance, at least in part.

There are so many answers to this question, depending on signal speed, rise time, etc etc dose it require termination etc.

marce said:

There are so many answers to this question, depending on signal speed, rise time, etc etc dose it require termination etc.

Click to expand...

Please give me one or two good solutions. Thanks!

---------- Post added at 12:10 ---------- Previous post was at 12:09 ----------

FvM said:

This may be difficult with resonable trace parameters. You would rather reduce the source impedance, at least in part.

Click to expand...

How to reduce the source impedance? Thanks!

How to reduce the source impedance?

Click to expand...

That depends on the source. The problem is, that you didn't give much informations about your circuit, as marce already mentioned.

With more info I could refer to Chapter 6 in High Speed Digital Design, Howard Johnson. There are a multitude of termination solutions, series, mid point parallel, end parallel, ac, dc, thevorin etc any of which may work and just as important may not work.

Dear Marce & FVM,

Thank you for all the help so far.

Details on my circuit:-
The driver is one of the output pins for 74ACT244 Octal Buffer/Line Driver.
Both the input pins are from the control pins (A, B & C) of the MAX4617.
Attached datasheets.

Please advice on how should the trace be designed from one output pin of 74ACT244 to two control pins (A, B, C) on separate MAX4617 ICs.

Best Regards,
Newbie101

Considering the driving device, and probable switching speed (lowish I presume) either a dasiy chain or parallel connection would probably work, it has enough current drive.
In situations like this I would get the engineers opinion, then probably use my SI tool to check different options (I have the tool, so mite as well use it.) if I had any doubts.
Depending on layout topology would determine my choice. If the two MAX4167s are near each other I would probablu use daisy chain, if they are seperated I would use parallel.

---------- Post added at 10:45 ---------- Previous post was at 10:42 ----------

Considering the driving device, and probable switching speed (lowish I presume) either a dasiy chain or parallel connection would probably work, it has enough current drive.
In situations like this I would get the engineers opinion, then probably use my SI tool to check different options (I have the tool, so mite as well use it.) if I had any doubts.
Depending on layout topology would determine my choice. If the two MAX4167s are near each other I would probablu use daisy chain, if they are seperated I would use parallel.
More info on the schematic and general layout would help, as without the intimate knowledge I can only give vauge suggestions.

For single ended TTL or CMOS logic signals, end termination is rarely an reasonable option due to it's high power dissipation, expect for very long cables. If termination is needed at all, a source side series termination is more appropriate. It's frequently used with high speed logic devices like FPGA. Programmable driver impedance is used to match the trace impedance, for higher impedances, external series resistor are placed.

For your circuit, I would ask for the trace length first. Impedance matching is particularly critical for edge sensitive signals (clocks) where reflections may cause ringing edges and double clocking. For level sensitive signals fed to rather slow devices as the said CMOS analog multiplexer, it's most likely not required.

Dear Marce & FvM,

Thanks so much for help.

Both receivers are quite far apart.
If routed in parallel, the trace length is around 5000mils from driver to each receiver.
If routed daisy-chained, trace length to first receiver would be 5000mils and to next receiver 7000mils.
Given these trace lengths, will it be necessary to include termination?

The other problem is that all 8 output pins from the 74ACT244 are similarly connected to respective receiver pins (which might cause total current to be too high). The series termination with parallel traces sounds good, but I can't find the driver output resistance from the datasheet. Please help find this.

Best Regards,
Newbie101

5" (125 mm) isn't large distance in my opinion. A driver series termination that halfway matches the trace impedance would be a good solution.

CMOS drivers have a non-linear I/V characteristic, in so far is estimating an output impedance always a simplification. It can be best extracted from an output characeristic, unfortunetael it's rarely given in datasheets. The current drive strength numbers suggest an typical output impedance of ACT244 around 25 to 30 ohm, by adding a series resistor of 39 to 56 ohm, it can be best matched to a typical single ended PCB trace with 70 to 90 ohm characteristic impedance. Checking the waveform at the load (preferably with a low capacitance probe) is the best way to validate the impedance matching.

P.S.: As a disadvantage, source side termination achieves good waveforms only at the load. It's still reasonable to use it with tapped transmission lines to reduce overshoots due to signal reflections. But you'll get a step waveform at the driver and in the middle of the transmission line. When driving two lines, separate series resistors should be used to reduce end-to-end reflections.

If you can get hold of Howard Johnson/Martin Graham "High speed digital design" do so, chapter 6 covers all the various options of termination. I have studied this chapter extensively over the last few months, in conjuntion with learning and using my signal integrity verification software.
I had a similar problem with a jtag clock going to multiple devices, in that instance I used a clock buffer device and AC biased end termination. The 244 device is a bus driver so should be able to drive the busses with basic termination. What speed will it be switching at? This is why I love SIV software, you can remove the guess work (all be it educated guess work) from the design and try different solutions untill you find the best one.

There are many termination solutions to choose from, heres some interesting notes on the various options.
**broken link removed**
https://www.ultracad.com/mentor/transmission line terminations.pdf
**broken link removed**
The Basics of Signal Integrity, Part I
https://web.cecs.pdx.edu/~greenwd/xmsnLine_notes.pdf

Dear Marce & FvM,

Thanks again for all the help.

I'm going for the series termination with separate traces. Will try to run some simulation to confirm resistor value.
Hope there will be enough space on PCB to add the extra resistors.

Best Regards,
Newbie101

** Attached IMHO a good article on termination I'm currently reading **