ModelSim- RAM simulation error

Dear all,

I write RAM code and compile it in Quartus2 successfully. But, when I compile it in ModelSim an error occurs. Can anyone help and tell me where Iam missing. Below is my code.
--------------Main code------------------
library ieee;
use ieee.std_logic_1164.all;

entity memory2 is
generic (N: integer :=8;
M: integer :=4);
port (clk, write: in std_logic;
address: in integer range 0 to 2**M-1;
data_in: in std_logic_vector (N-1 downto 0);
data_out: out std_logic_vector (N-1 downto 0));
end memory2;

architecture memory2 of memory2 is
type memory is array (0 to 2**M-1) of std_logic_vector (N-1 downto 0);
signal ram: memory;
begin
process (clk)
begin
if (clk'event and clk='1') then
if (write'event and write='1') then
ram(address)<=data_in;
end if;
end if;
end process;
data_out<=ram(address);
end memory2;

-------------------Testbench------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity memory2_tb is
end;

architecture bench of memory2_tb is
constant N: integer :=8;
constant M: integer :=4;

component memory2
generic (N: integer :=8;
M: integer :=4);
port (clk, write: in std_logic;
address: in integer range 0 to 2**M-1;
data_in: in std_logic_vector (N-1 downto 0);
data_out: out std_logic_vector (N-1 downto 0));
end component;

signal clk, write: std_logic;
signal address: integer range 0 to 2**M-1;
signal data_in: std_logic_vector (N-1 downto 0);
signal data_out: std_logic_vector (N-1 downto 0);

constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;

begin

uut: memory2 generic map ( N => 8,
M => 4)
port map ( clk => clk,
write => write,
address => address,
data_in => data_in,
data_out => data_out );

stimulus: process
begin
data_in<= "11111110",
"01100000",
"00011011",
"11001011";
wait for 150ns;

stop_the_clock <= true;
wait;
end process;

clocking: process
begin
while not stop_the_clock loop
clk <= '1', '0' after clock_period / 2;
write <= '1', '0' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;

end;

This error occur when I compile testbench code in ModelSim:
**Error: C:/altera/RAM_test/memory2_tb.vhd(41): Delay in signal assignment must be ascending.
Many thanks.

Hi, check changing the array assignment to as below. (Adding Parenthesis)
data_in<= ("11111110",
"01100000",
"00011011",
"11001011");