gmish27
Member level 1
what's wrong with the following code:
module test
(
input a,b,c,
output y
);
wire x;
assign y = a & x;
assign x = b & c;
endmodule
it synthesizes and simulates too but I read their will be a mis-match between the pre and post synthesis. care to explain???
module test
(
input a,b,c,
output y
);
wire x;
assign y = a & x;
assign x = b & c;
endmodule
it synthesizes and simulates too but I read their will be a mis-match between the pre and post synthesis. care to explain???