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  1. #1
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    gmish27's Avatar
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    problem with assign in verilog

    what's wrong with the following code:

    module test
    (
    input a,b,c,
    output y
    );

    wire x;
    assign y = a & x;
    assign x = b & c;

    endmodule

    it synthesizes and simulates too but I read their will be a mis-match between the pre and post synthesis. care to explain???

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  2. #2
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    Re: problem with assign in verilog

    Just wanted to know where u have read or can you attach the doc which supports your statement.

    I really don't see any issue with the above code.



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  3. #3
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    Re: problem with assign in verilog

    I also tried with vcs and did not found any problem and I also did not see any change after synthesis. its remains 2-input AND.



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  4. #4
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    Re: problem with assign in verilog

    Not in this case. If you try using non-blocking assignments in always loop with clock you may see the difference.



  5. #5
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    Re: problem with assign in verilog

    yes, try to use non-blocking method in you assign statement!



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