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32K point FFT Core for DVBT 2 Receiver

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Gem88

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we are working on 32K point fft core for DVBT 2 receiver. we are implementing it via verilog on fpga.
the research papers shows us that it have been implemented on Virtex 5 board, but we are trying to design an algorithm that would help us implement it on Spartan 3E kit.

is it possible to implement it on spartan 3e?
 

kindly can any one justify this claim:

"it is easy to develop algorithms for fft"
 

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