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  1. #1
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    Signal integrity in CADSTAR ????

    Is there any one who has used Signal integrity in CADSTAR?

    As i am facing problem in doing simulation an error
    as follows
    @Simulation returned a fail with C:/ program / zuken

    Regard's
    Antarveena

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  2. #2
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    Re: Signal integrity in CADSTAR ????

    Yes I do.
    Can you supply a bit more info please:
    What you were simulating, and when does the error occur.



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    Re: Signal integrity in CADSTAR ????

    when i creating daisy chain model in the scenario editor and simulating the
    model then rather then ,opening simulating window its showing such error.

    Regard's
    Antarveena



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    Re: Signal integrity in CADSTAR ????

    Had a quick go at trying to recreate the problem, but havn't managed yet. I have seen this message but not for a while. I suspect it either cant find device model or pin model, it is somthing that means it cant do a simulation, but it is trying to isolate the main fator. I will have a play this weekend as I am doing some simulations.
    What I have done with my set up is laod and import the IBIS models for all our active devices and added a link to the Cadstar parts library, so that all parts are mapped to the relevant device models.



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    Re: Signal integrity in CADSTAR ????

    Hi Marce

    I have query that i have cadstar8.0 and can i do the Post SI in hyperlynx6.0? If so can you please tell me the process.

    Regard's
    Antarveena

    ---------- Post added at 08:10 ---------- Previous post was at 07:50 ----------

    I mean how to transfer .pcb file to .hyp file?
    Regard's
    antarveena



  6. #6
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    Re: Signal integrity in CADSTAR ????

    I use Cadstars own Si tool, but belive there hyperlynx will accept Cadstar data. I haven't done it myself, but would suspect that hyperlynx will import one of the Cadstar output formats (probably the CADIF; *.paf format).



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  7. #7
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    Re: Signal integrity in CADSTAR ????

    Hi Marce

    CADIF is not the supported by hyperlynx , actually i am trying the self teach chapter of the Cadstar8.0 and after doing the scenario editor when select the topologies it works fine , but when do the simulation it again shows the above mentioned error

    Regard's
    Antarveena



  8. #8
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    Re: Signal integrity in CADSTAR ????

    I belive you have to get a translator, I do know it is the way to get Cadstar design in there cos I have had it done last year and we sent a *.paf file (Cadif) to the simulation house, who use hyperlynx.



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