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  1. #1
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    from verilog to vhdl code

    Please how can i change the following verilog code to vhdl code to understand it. I don't know the meaning of the verilog syntax:


    module md(clk, rst, k_in, v_out, v_out_offset);
    input clk, rst;
    input [23:0] k_in;
    output [3:0] v_out, v_out_offset;

    reg [3:0] v_out,v_out_offset;
    reg [23:0] D1, D2, D3;
    wire [23:0] sum1, sum2, sum3, sum4, sum5, sum6, sum7, v_fd, v_fd_neg;

    assign sum1 = k_in + v_fd_neg;
    assign sum2=sum1 + D1;
    assign sum3=D1 + D2;
    assign sum4=D2 + D3;
    assign sum5=D2 + {D2[23],D2[23:1]};
    assign sum6={D1[22:0],D1[0]} + {D3[23],D3[23:1]} +sum5;
    assign sum7=sum6[23:19] + 1'b1;

    always@(posedge clk or posedge rst)
    begin
    if(rst) D1<=24'h0;
    else D1<=sum2;
    end

    always@(posedge clk or posedge rst)
    begin
    if(rst) D2<=24'h0;
    else D2<=sum3;
    end

    always@(posedge clk or posedge rst)
    begin
    if(rst) D3<=24'h0;
    else D3<=sum4;
    end

    always@(posedge clk or posedge rst)
    begin
    if(rst)
    begin
    v_out<=4'b0000;
    v_out_offset<=4'b1000;
    end

    else
    begin
    v_out<=sum7[4:1];
    v_out_offset<=sum7[4:1]+ 4'b1000;
    end

    end

    assign v_fd=~sum7[4:1]+1'b1;
    assign v_fd_neg={v_fd[3:0],20'h00000};

    endmodule

  2. #2
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  3. #3
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    Re: from verilog to vhdl code

    hi...
    if you want to understand then change the following codes from verilog to vhdl
    In Verilog In Vhdl
    wire = signals
    always@ = process
    (assign) = (<=)

    module(inputs, outputs) =entity in's,out's
    example
    input [23:0] k_in; = k_in :in std_logic_vector(23 downto 0);

    you can refer above links also for more clear



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    Re: from verilog to vhdl code

    if u familiar with vhdl, it is not so hard to understand the verilog..
    check this out --> WELCOME TO WORLD OF ASIC



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  5. #5
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    Re: from verilog to vhdl code

    i think you can easily have a quick learn to verilog.it not much different .

    i learned vhdl first ,but now i use verilog more . they are very similar .



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    Re: from verilog to vhdl code

    in the code above i don't understand theses syntax:

    assign sum5=D2 + {D2[23],D2[23:1]};
    assign sum6={D1[22:0],D1[0]} + {D3[23],D3[23:1]} +sum5;
    assign sum7=sum6[23:19] + 1'b1;

    can you please explain me the meaning

    Thks a lot
    noura



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    Re: from verilog to vhdl code

    Verilog Concatenation Operator
    Verilog Concatenation Operator



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  8. #8
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    Re: from verilog to vhdl code

    Quote Originally Posted by noura7 View Post
    in the code above i don't understand theses syntax:

    assign sum5=D2 + {D2[23],D2[23:1]};
    assign sum6={D1[22:0],D1[0]} + {D3[23],D3[23:1]} +sum5;
    assign sum7=sum6[23:19] + 1'b1;

    can you please explain me the meaning

    Thks a lot
    noura
    assign sum5=D2 + {D2[23],D2[23:1]}; //mean :i think you don't understand the connection symbol{ }. because the verilog support bit operation,so{D2[23],D2[23:1]}; means a new data contruct by D2[23],D2[23:1].the new data's highest bit is D2[23],and the rest is D2[23:1].

    an easy example:
    a="abcdef"; a,b..f means '1' or '0';
    the {a[5],a[5:1]} is "aabcde".



  9. #9
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    Re: from verilog to vhdl code

    Thank you Mr. LB for your response. Really i dont undertsatnd. if i want for example sum5=0.5*D2 how can be the syntax in verilog code.

    thks a lot
    Noura



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    Re: from verilog to vhdl code

    Quote Originally Posted by noura7 View Post
    Thank you Mr. LB for your response. Really i dont undertsatnd. if i want for example sum5=0.5*D2 how can be the syntax in verilog code.

    thks a lot
    Noura
    sorry ,FPGA does not support floating operation. in FPGA world ,you can just do all your work with '1' or '0'.

    in fact you caculate floating numbers in dsp or mcu ,because in the dsp or mcu ,we use some Algorithm instead of direct floating operation,with make you act as operating floating caculate.

    we usually use 2c code example do the DSP.

    maybe you can check a book,《digital signal processing with field programmable gate arrays》 written by Uwe Meyer-Baese。or you can google,there lots of good papers on the Internet .

    ---------- Post added at 05:05 ---------- Previous post was at 04:53 ----------

    Quote Originally Posted by noura7 View Post
    Thank you Mr. LB for your response. Really i dont undertsatnd. if i want for example sum5=0.5*D2 how can be the syntax in verilog code.

    thks a lot
    Noura
    in fpga,we do sum5=0.5*D2 like this :I take another common example sum5 = 0.1258 * D2 .

    first we expend 0.1258 by mutiplying 2^n( n is base on your Accuracy ),n=10 eg. so 0.1258 multiply 1024 equals 128.8192 we round for 129 .
    then we do sum5 = 0.1258 * D2 by sum5 = 129 * D2 .
    at last ,we get a product ,and we must cut the last 10 bits ( equal to divide 1024 ).

    so ,that is the result . of course ,we can keep the gain if needed.



  11. #11
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    Re: from verilog to vhdl code

    Here it goes .....
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    
    entity md is
      port (
        clk          : in  std_logic;
        rst          : in  std_logic;
        k_in         : in  std_logic_vector(23 downto 0);
        v_out        : out std_logic_vector(3 downto 0);
        v_out_offset : out std_logic_vector(3 downto 0));
    end md;
    
    architecture behave of md is
      signal  D1, D2, D3: std_logic_vector(23 downto 0);
      signal  sum1, sum2, sum3, sum4, sum5, sum6, sum7, v_fd, v_fd_neg : std_logic_vector(23 downto 0);
    begin  -- behave
    
      sum1 <= k_in + v_fd_neg;
      sum2 <= sum1 + D1;
      sum3 <= D1 + D2;
      sum4 <= D2 + D3;
      sum5 <= D2 + (D2(23) & D2(23 downto 1));
      sum6 <= (D1(22 downto 0) & D1(0)) + (D3(23) & D3(23 downto 1)) + sum5;
      sum7 <= ("0000000000000000000" & sum6(23 downto 19)) + 1;
    
      process (clk, rst)
      begin  -- process
        if rst = '1' then                   -- asynchronous reset (active high)
          D1           <= (others => '0');
          D2           <= (others => '0');
          D3           <= (others => '0');
          v_out        <= (others => '0');
          v_out_offset <= (others => '0');
        elsif clk'event and clk = '1' then  -- rising clock edge
          D1           <= sum2;
          D2           <= sum3;
          D3           <= sum4;
          v_out        <= sum7(4 downto 1);
          v_out_offset <= sum7(4 downto 1)+ "1000";
        end if;
      end process;
    
      v_fd     <= ("00000000000000000000" & not(sum7(4 downto 1))) + 1;
      v_fd_neg <= v_fd(3 downto 0) & "00000000000000000000";
      
    end behave;



  12. #12
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    Re: from verilog to vhdl code

    Quote Originally Posted by nand_gates View Post
    Here it goes .....
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    
    entity md is
      port (
        clk          : in  std_logic;
        rst          : in  std_logic;
        k_in         : in  std_logic_vector(23 downto 0);
        v_out        : out std_logic_vector(3 downto 0);
        v_out_offset : out std_logic_vector(3 downto 0));
    end md;
    
    architecture behave of md is
      signal  D1, D2, D3: std_logic_vector(23 downto 0);
      signal  sum1, sum2, sum3, sum4, sum5, sum6, sum7, v_fd, v_fd_neg : std_logic_vector(23 downto 0);
    begin  -- behave
    
      sum1 <= k_in + v_fd_neg;
      sum2 <= sum1 + D1;
      sum3 <= D1 + D2;
      sum4 <= D2 + D3;
      sum5 <= D2 + (D2(23) & D2(23 downto 1));
      sum6 <= (D1(22 downto 0) & D1(0)) + (D3(23) & D3(23 downto 1)) + sum5;
      sum7 <= ("0000000000000000000" & sum6(23 downto 19)) + 1;
    
      process (clk, rst)
      begin  -- process
        if rst = '1' then                   -- asynchronous reset (active high)
          D1           <= (others => '0');
          D2           <= (others => '0');
          D3           <= (others => '0');
          v_out        <= (others => '0');
          v_out_offset <= (others => '0');
        elsif clk'event and clk = '1' then  -- rising clock edge
          D1           <= sum2;
          D2           <= sum3;
          D3           <= sum4;
          v_out        <= sum7(4 downto 1);
          v_out_offset <= sum7(4 downto 1)+ "1000";
        end if;
      end process;
    
      v_fd     <= ("00000000000000000000" & not(sum7(4 downto 1))) + 1;
      v_fd_neg <= v_fd(3 downto 0) & "00000000000000000000";
      
    end behave;
    good man,... i think you can not do all for him.



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  13. #13
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    Re: from verilog to vhdl code

    Thanks a lot you Mr. nand_gates for the code.
    I con not resolve until now the problem of multiplication a signal with a coefficient. how can i write the syntax like these? D1, D2 and D3 are signals.

    sum3 <= D1 + D3*(-3.6139e-004);
    sum6 <= D1*(1.9821) + D2*(1.5040) + D3*(0.4131);



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    Re: from verilog to vhdl code

    One possible not practical crude solution will be to use look-up table memory for each multiplication!
    Second approach will be use floating point /fixed point multiplier IP.
    Third approach use soft-core CPU and do the multiplication in software.
    Fourth approach simplify the equations as follows

    sum6 <= D1*(1.9821) + D2*(1.5040) + D3*(0.4131);
    This can be written as
    sum6 <= D1*2 + (D2+D2/2) + D3/2; here I am approximating 1.9821 ~2.0 1.5040 ~ 1.5 and 0.4131 ~ 0.5

    Hope this helps!



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    Re: from verilog to vhdl code

    Quote Originally Posted by nand_gates View Post
    One possible not practical crude solution will be to use look-up table memory for each multiplication!
    Second approach will be use floating point /fixed point multiplier IP.
    Third approach use soft-core CPU and do the multiplication in software.
    Fourth approach simplify the equations as follows

    sum6 <= D1*(1.9821) + D2*(1.5040) + D3*(0.4131);
    This can be written as
    sum6 <= D1*2 + (D2+D2/2) + D3/2; here I am approximating 1.9821 ~2.0 1.5040 ~ 1.5 and 0.4131 ~ 0.5

    Hope this helps!
    thanks nand for your response. I must use these coefficients with this precision. Can you please help me how can i built a fixed point multiplier IP and how can i apply it in the main vhdl code.

    thanks a lot,
    Noura



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