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Factors affecting the PLL output clock quality

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nishanthmv

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Hi,
It would be great if anyone could help me in understanding the what factors can affect the PLL output clocks' quality (like jitter, duty cycle variation etc) in an SoC.

Can I use PLL input clock (driven by ext crystal/osc) directly to drive internal logic when the device needs to be put in a kind of quasi-sleep mode(when PLL is to be shut down)?

If I use PLL input clock to drive some part of internal logic (along with PLL), can it cause issues in PLL output clock?

Appreciate your help.

--
Nishanth
 

Hi Nishant,

On your specifc questions here is answer, hope this will help:

Code: 
what factors can affect the PLL output clocks' quality

I think major factor to infuence above are

1. qaulity of VDD / VSS. It means how much noise can be there on this.
2. Internal structure / design of PLL.

Code: 
Can I use PLL input clock (driven by ext crystal/osc) directly to drive internal logic

Yes you can use. Off cource CLKIN going to PLL in such case should have not become noisy in this case. It meanse you need to have seperate route for clock going to PLL and clock used anywhere else.

I hope this will help :)
 

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If you want , send a email to me . i'll send my methods to your emails!
 

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