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This circuit is in analog design. M2 and M3 are always on. What is the function of M2 and M3? Could they improve the performance? And what performance? Thanks
Put also the dimensions into the schematic. If the two static MOS are long channnel I think it is for limiting rise/fall time without having the capacitive gate load on the switch input. So using minimum at the switch and long channel for the static MOS.
A complimentry output stage. Just as a matter of intrest the vcc power supply points . Is one of them positive and the other a negative voltage. If this is the case then the output stage would provide a near faithfull duplication of the input but with a great deal of power.
I do not think it is a complementary output stage because the output voltage range where the output impedance is high is relative small. Could you answer what type of input signal is normally applied?
I agree with rfsystem, it would be stupid to use this circuit as an output stage; most likely it is just an inverter with tweeked rising-edge and falling-edge propagation delays...
staric wrote <This circuit is in analog design. M2 and M3 are always on. What is the function of M2 and M3? Could they improve the performance? And what performance? >
if M2 and M3 are always on,the circuit is a inverter.
M2 and M3 reduce the output voltage range.
staric wrote <This circuit is in analog design. M2 and M3 are always on. What is the function of M2 and M3? Could they improve the performance? And what performance? >
if M2 and M3 are always on,the circuit is a inverter.
M2 and M3 reduce the output voltage range.
From my point of view,
It just acts as a invertor.
M2 & M3 are used to prevent the input signal from coupling to the output.
Charge feedthrough will occur due to capacitors Cgd if M2 and M3 do not exist.
I agree with totoro...
This technique is mainly used to avoid the charge feedthrough...
You can see the result in the waveform simulated. red waveform without the M2 and M3 has more glitch at the transition point but not the green waveform (with M2 and M3).
This is mainly used in current steering DAC design( just below the switch) to reduce the glitch energy.
IF try simulate different cload from small to large.
the simulation will tell.
1. clk feedthrouth by cgd,not the reson,why dont you just add to cload
2. charge injection by channel ,YES.It is different but....
if the circuit is mainly digital output...accurate maynot a mainly issue
if the circuit is mainly analog,the bias will not choose vdd/vss,it can choose a better point for Rout or distortion consideration in all signal swing
1.the peak di/dt is different
2.current inject to substate is different
3.the noise to power line is different
4.the speed/power is different
Glitch is more of a reliability issue than accuracy. But you are right in divining that the circuit is not used in analog applications. Else the CG transistor switching from triode to active region will introduce quiet a bit of non-linearity. Even I agree that the extra CG transistors just provide a low impedance node for the charge injection, thus isolating the output.
This is nothing but an invertor and is common in I/O circuit design.
Primarily used for situations where the X'tors are LV devices and you want to operate of higher power supply.
Hi, all
This question is just like my question. There is a cascode feedback amp with a complementary transconductance stage as illustrated in the Fig, it is used for better tradeoff between noise performance and linearity at low power consumption.
Can anyone tell me about the operation principle of this circuit, or any link to talk about it ?
Thanks a lot!
I think the two circuits are different. The first one should be a inverter with limited switching current. In some application, if the voltage of "IN " changes very slowly, a big current will flow in the inverter during transition. So the current should be limited.
M2 and M3 with big L/W should behave as resistors.
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