Transistor-Level reliability simulations

ultrasim nbti hci model

I need to do some MOS Transistor-Level reliability simulations. Does someone has information about this kind of simulations.

Thanks.

bastos

Use PSPICE to simulink MOS level. There are 3 level of SPICE. You can check the accuracy of each level.

No, the problem is not that one.

I want to simulate the aging of each transistor, due to hot electron effect and negative bias temperature instability. These effects cause a shift in the VT of the MOS and causes asymmetry in device I-V characteristics.
This is problematic in 90nm and lower tech. devices.

Bastos

I think there are some new tools supplying this kind of simulation. For regular simulation there is only a workaround.

1. Limit to a smasll circuit or to a small focus to some aprt of the circuit.
2. Simulate a regular complete operating cycle
3. Process the voltages and the currents in the devices though a aging model
4. Adjust individual process/model parameter to the aging value.

The other way is

1. Make around each aging sensitive device a subcircuit
2. Make a behaviour which sense the aging critical terminal values
3. Calculate aging while running simulation in the behaviour
4. Feed the calulate aging into equivalent sources

The only one simulator that has these features is Hsim5plus.

Bastos

Bastos,

I think that Cadence's Ultrasim also simulates that.

How is built the aging model ?

Bastos

As far as I know, there exist some equations which tells about the aging effect on Vt & I(sat).
But I do not know, if a model exist for this.

Hi Bastos,

The new version of Eldo also simulates aging. However, it's up to you to characterize the model.

More on this later. (I gotta go)

I remember berkeley had some papers on such a simulator.

Check out Chemming Hu's group at UC berkeley.

The idea is to do aging sims (degradation in the mos char) and see if the I changes by more than 10% in any block over 7yr/15 yr

This is an unusual thing to do. During a "Process Qualification" the FAB will carry out the long term reliability testing of the transistors. These are accelerated by using much higher Vdd and temperatures than the transistor will ever see. For Hot Carrier, modelling this would require a 3D simulator and very accurate detials of doping profiles beneath the LDD spacer of every transistor. It would also require detailed knowledge of electron trapping behaviour of the gate oxide - something that would be specific to the manufacturing. The FAB will normally qualify the process when HCI stressing does not degrade the gm of the device by more than 10% over 10 years. So if you need to simulate what happens to the transistor after 10 years of use, the degradation can assumed to be 10%. This is just for HCI - other mechanisms of degradation exist. The testing of these mechanisms are controlled by JDEC (or something) standards, so documentation should be available somewhere.

I think that you 'd better ask your process interface if they have a model for aged transistors. You may probably have to do it yourself based on a slow case model or so, to include aging effects.
By the way, which effects hsim5+ include in its simulation ?

Thanks for all the info. I'm trying to get some info from fab.

In hsim5+ is model HCI and NBTI.

Bastos

there's a tool called "btabert" which could simulate the reliability of semiconducotor.you also need another tool which is called "realsim pro" to exact some parameters needed for "btabert".