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    phase selector verilog-A model

    Hi, all:

    I need your help. I want to write verilog-A model about phase selector. The phase selector theory is: there are eight phase clock input, and the phase difference is 0.125*2*pi*Fref. I need to select one of them output.
    When A=-1, the output is a phase that lag the current one
    A=0, the output is current phase.
    A=1, the output is a phase lead the current one by two
    A=2, the output is a phase lead the current one by one.
    I write the verilog-A model like this:


    // VerilogA for USB20, PHASE_SELECT, veriloga

    `include "constants.vams"
    `include "disciplines.vams"

    module PHASE_SELECT(P, IN0, IN1, IN2, IN3, OUT);
    output OUT;
    input [0:7] P;
    input IN0, IN1, IN2, IN3;
    voltage [0:7] P;
    electrical IN0, IN1, IN2, IN3, OUT;


    parameter real tdel = 0 from [0:inf);
    parameter real trise = 0 from [0:inf);
    parameter real tfall = 0 from [0:inf);

    real IN;
    integer i;
    analog begin
    @ ( initial_step ) begin
    i=1;
    IN = V(IN0) + 2*V(IN1) + 4*V(IN2) -8* V(IN3);
    end
    case (IN)
    2: begin if (i-2>=0)
    i= i-2;
    else i= 8+i-2;
    end
    1: begin if (i-1>=0)
    i= i-1;
    else i= 8+i-1;
    end
    0: i=i;
    -1: begin if (i+1<=7)
    i= i+1;
    else i=-8+i+1;
    end
    endcase

    V(OUT) <+ transition(P[i], tdel, trise, tfall);
    end
    endmodule

    Whatever I setup the IN0-IN3, the output is zero without any change. Can anyone help me? Thanks.

    ---------- Post added at 10:04 ---------- Previous post was at 09:32 ----------

    My cadence version is 5.10.41, so I can not use "genvar" command.

    Maybe it caused by this.

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  2. #2
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    Re: phase selector verilog-A model

    Your block is not sensitive to the input changes and therefore once you finish the @initial_step your block stays inactive. You need to detect changes in the control word and in the input clock and transfer them to the output. You can, for instance, use the function @cross() on your inputs.



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    Re: phase selector verilog-A model

    Thanks, JoannesPaulus. I don't know how to use a vector P[0:7] as input, indeed. Whether You mean that I need to use cross function instead of if function?
    And another question is //V(OUT) <+ transition(P[i], tdel, trise, tfall);// I want to send P[i] to output, is it right? thanks again.



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    Re: phase selector verilog-A model

    Use @timer().

    @(timer(period/2+phase, period/2))
    state= !state;
    V(vout) <+ V(vdd,vss) * transition(state, 0.0, tr, tf);
    end
    Also see The Designer's Guide Community Forum - verilog A code for 16:1 mux


    Quote Originally Posted by nichocheng View Post
    [/COLOR]My cadence version is 5.10.41, so I can not use "genvar" command.
    What do you wan to mean ?
    Version of Cadence DFII has no relation regarding "genvar" at all.
    Last edited by pancho_hideboo; 29th April 2011 at 14:26.



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    Re: phase selector verilog-A model

    Verilog-A uses "generate" not "genvar".

    If I understand pancho_hideboo's code, he is generating an autonomous clock with a given phase but he is not muxing one of the input phases out.
    In my opinion, you need to check for changes of either P or IN and then select the correct output using a case statement.



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    Re: phase selector verilog-A model

    Quote Originally Posted by JoannesPaulus View Post
    Verilog-A uses "generate" not "genvar".
    Wrong.

    "generate" is obsolete.
    Currently we have to use "genvar".



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    Re: phase selector verilog-A model

    Wrong.
    My cadence version is 5.10.41, so I can not use "genvar" command.
    "genvar" is used in cadence 6.1



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    Re: phase selector verilog-A model

    Quote Originally Posted by JoannesPaulus View Post
    Wrong."genvar" is used in cadence 6.1
    Very wrong.

    You can't understand Cadence tools at all.

    "5.10.41" is version of DFII.

    We can use MMSIM(=Spectre) of version 5.X and 6.* in DFII of 5.10.X.

    "genvar" is used in any of MMSIM 5.X and 6.X.
    But "genvar" can't be used in older Spectre such as 4.4.X.

    Generally Spectre of version 4.4.X is not used in DFII of 5.10.X intensively.
    The Designer's Guide Community Forum - simulating phase noise of differential LC-VCO in spectre
    Last edited by pancho_hideboo; 29th April 2011 at 18:01.



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    Re: phase selector verilog-A model

    I stand corrected on the versions and all the rest.
    At any rate, from the bit of information nichocheng gave I believe he is using an older version of spectre - possibly 4.4.x - with DFII 5.10.x (I had the same set-up at a start-up a few years back).

    nichocheng, what what is your set-up?
    Last edited by JoannesPaulus; 29th April 2011 at 18:21. Reason: mispelling



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    Re: phase selector verilog-A model

    See http://www.designers-guide.org/Veril...MS-2.1-pub.pdf

    "genvar" is available even in this relative old LRM, Version 2.1 (Jan 2003).

    I don't remember correctly, but "genvar" is available after Spectre 4.4.6.



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