Continue with fifo problems

Problems with a FIFO

I continue with problems in my FIFO... The problem its when i want to read positions...


1st - OPTION:

--8 bits 16 fields FIFO.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FIFO_TX is
port ( clk : in std_logic;
en_fifoTX : in std_logic;
read_en : in std_logic;
write_en : in std_logic;
salida : out std_logic_vector(7 downto 0); -- Fifo OUTPUT
entrada : in std_logic_vector (7 downto 0); -- FIFO INPUT
vacia, llena: out std_logic -- Vacia means emtpy, Llena means full;
);
end FIFO_TX;

architecture Behavioral of FIFO_TX is
type memory_type is array (0 to 15) of std_logic_vector(7 downto 0);
signal memory : memory_type :=(others => (others => '0'));
signal p_read,p_write : integer range 0 to 15:=0; -- Pointers (reading/writing)
begin
process(clk,write_en,p_write,en_fifoTX)
begin
if(clk'event and clk='1') then
if (en_fifoTX='1') then -- If FIFO enabled
if (write_en ='1') then -- if Writing enabled
if (p_write=0) then
vacia<='1'; -- vacia (=emtpy)
else vacia<='0';
end if;
memory(p_write) <= entrada; -- We are writing in fifo the INPUT vector value
if(p_write = 15) then -- IF pointer its in last position...
llena<='1'; -- ... Fifo is full
p_write <= 0; -- and pointer its set to first FIFO position
else
p_write <= p_write + 1; -- ELSE, we continue increasing the pointer to write into next FIFO position
llena<='0';
end if;
end if;
end if;
end if;
end process;

PROBLEMS START HERE




process(clk,read_en,p_read)
begin
if(clk'event and clk='1') then
if (read_en ='1') then -- if reading enabled
salida <= memory(p_read); -- current position its read
if(p_read = 15) then -- if we are in last FIFO position ...
p_read <= 0; -- we set the pointer to 0
else p_read <= p_read + 1; -- else we continue reading next fifo position
end if;
else salida<=(others=>'Z'); -- Apunta a la siguiente direccion de memoria.
end if;
end if;

end process;
end Behavioral;
------------------------------------------------

When i do this, "salida" depends of the Fifo clock (Salida its the Output vector), so when I do the RTL view, a "Salida Register" appears.
I want to erase this register so i have to make the "salida output" non depending of clk. So i tried this:


process(clk,read_en,p_read)
begin
if (read_en ='1') then
if(clk'event and clk='1') then
if(p_read = 15) then
p_read <= 0;
else p_read <= p_read + 1;
end if;
end if;
salida <= memory(p_read);

else salida<=(others=>'Z');
end if;
end process;

end Behavioral;


When I do this, FIFO worked but when i tried to add it to my sistem, a lot of warnings appeared due to this line:

signal memory : memory_type :=(others => (others => '0'));

The errors are like:

Warning (14130): Reduced register "FIFO_TX:FifoTransmision|memory~102" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "FIFO_TX:FifoTransmision|memory~118" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "FIFO_TX:FifoTransmision|memory~134" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "FIFO_TX:FifoTransmision|memory~150" with stuck data_in port to stuck value GND


So i dont know how to fix my fifo. Any suggestions? Thank you!

---------- Post added at 12:58 ---------- Previous post was at 12:48 ----------

doing:

signal memory: memory_type; runs well. I dont know why i cannot initialize RAM to 0 :\