Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

parallel in parallel out memory design in verilog

Status
Not open for further replies.
A

alexjpaul

Newbie level 4
Joined
Apr 17, 2011
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,325
Am writting verilog code for 3d-dwt. in this i require a memory which should get 512 input 0f each10 bit parallely and it should give the output parallely...plz any one help me on this..and send the architecture to my mail

alexjchandra@gmail.com


thanks in advance
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top