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Help to read/write RAM in verilog?

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jpglotzer

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Hi, I'm trying to code a bubble sort algorithm to sort the values in my RAM based on size. I'm using the RAM 2-port megafunction in Quartus, and creating instances of the module in my main module.

The 2 port RAM megafunction has the following inputs/outputs:

module ram_2port (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);

Here is my code: (the 1st instance of the megafunction is to read the values of 2 addresses. If the first is bigger than the second, the values are swapped. The 2nd instance of the megafunction should do this; write the first value in the address of the 2nd and the 2nd value in the address of the first). I don't know why it's not working.



module question3(clock,j1,j2,q_a,q_b);

input clock;

output reg [7:0] j1,j2;

reg [4:0] i,j;

always @(posedge clock)
begin

for (i=5'd19; i>5'd0; i=i-5'd1)
begin
for (j=5'd1; j<i+5'd1; j=j+5'd1)
begin
j2<=j;
j1<=j-8'd1;

ram_2port ram1(j1,j2,clock,0,0,1,1,q_a,q_b);

if (q_a > q_b)
begin
ram_2port ram2(j1,j2,clock,q_b,q_a,0,0,0,0);
end

end
end
end

endmodule



Any help would be much appreciated! :D
 

your ram is a piece of hardware that has to be connected correctly
to other logic, it's not a function call you can execute inside
'for' loop;
below there is an example how to connect pieces together,
but the code does not solve your homework

Code: 
module ram_usage
(
   input  clock ....
   output data_out, ....
);

reg [4:0] counter;
  always @(posedge clock)
    counter <= counter + 1'b1;
// creation of hardware piece 'counter'

wire [7:0] qa, qb;  // connection between ram1 & ram2

wire [4:0] read_address  = counter;
wire [4:0] write_address = counter - 1'b1;
// when data from ram1 is ready, the counter will
// increase by 1, so write addr. has to be decreased
// to store data in ram2 at the same position

 ram_2port ram1 // instance of dual port ram, read-only
 ( .address_a(read_address),
   .address_b(read_address + 8'd8),   
   .clock(clock),
   .data_a(),     // no write, no input data connected
   .data_b(),
   .wren_a(1'b0), //no write, write enable grounded
   .wren_b(1'b0), //       - // -
   .q_a(qa),
   .q_b(qb)
  );
// pluging-in a piece of hardware 'ram_2port'

wire [7:0] da, db; // data input for ram2

  assign {da, db} = ( qa > qb ) ? {qa, qb} : {qb, qa};
  // swap if qa < qb  
  
 ram_2port ram2 // instance of dual port ram, write-only
 ( .address_a(write_address),
   .address_b(write_address + 8'd8),   
   .clock(clock),
   .data_a(da),
   .data_b(db),
   .wren_a(1'b1), //write always enabled
   .wren_b(1'b1), //       - // -
   .q_a(), // write only, data out not connected
   .q_b()  // it doesn't make sense of course
  );       // some extra logic needed to read-out data
           // when sorting is done
 
endmodule
----
have fun
 
Hi there,

Turns out, i can't instantiate the RAM module twice, calling it ram1 then ram2. This effectively means I'm reading from one RAM and writing to a second RAM. I've been advised to have one instantiation, and then just use a state machine to control whether it's reading or writing, but I'm running into some errors. I've got an idle state, an addresses state to vary which address to read from, a read state, a compare state, and a write state. I've been stuck on this for ages, and I think i just need a fresh set of eyes, so any help would be much appreciated! :D

Anyway, here's the code I'm using:


module question3(clock,start, q_a,q_b);

input clock; //declare clock
input start; //start button
output reg [7:0] q_a,q_b;

parameter [2:0] IDLE=3'b000, ADDRESSES=3'b001, READ=3'b010, COMPARE=3'b011, WRITE=3'b100;

reg [7:0] j=8'd0, data_a=8'd0, data_b=8'd0, max=8'd18, counter=8'd0;
reg [2:0] state=IDLE;
reg wren=1'b0;

ram_2port ram1(j,j+8'd1,clock,data_a,data_b,wren,wren,q_a,q_b);

always @(state)
begin
case (state)

IDLE: if (start==1)
begin
j=8'd0;
max=8'd18;
counter=8'd0;
state=READ;
end


ADDRESSES: if (j==max)
begin
max=max-8'd1;
j=8'd0;
counter=8'd0;
state=READ;
end
else
begin
j=j+8'd1;
state=READ;
end

READ: wren=1'b0;
state=COMPARE;


COMPARE: if (q_a > q_b)
begin
state=WRITE;
end
else
begin
if (counter==max)
begin
state=IDLE;
end
counter=counter+8'd1;
state=ADDRESSES;
end

WRITE: data_a=q_b;
data_b=q_a;
counter=8'd0;
wren=1'b1;
state=ADDRESSES;

endcase

end

endmodule
 

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