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[SOLVED] problem with a simple verilog code

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saad

saad

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Dear all, I am an intermediate-level verilog programmer. I was out of touch with Verilg programming so not really sure whats wrong with the following piece of verilog code.

Code: 
module single_bit(
    input [1:0] a,
    input index, 
    output out);
 	 reg out;
	 always @ index
		out = a[index];
endmodule

and the test bench:
Code: 
module test_single_bit;

	reg [1:0] a;
	reg index;
             wire out;

	single_bit uut (
		.a(a), 
		.out(out), 
		.index(index));

	initial begin
		#100
		a = 2'b01;
		index = 1'b0;
		
		#100;
		index = 1'b1;
		end      
endmodule

when I simulate it using xilinx ISE 13.1,

a remains 'zz' for all the time
index remains 'z' for all the time
out remains 'x' for all the time

Variables do no change their value even once. What could be the possible problem?

Thanks in advanced

Saad
 

I believe you're trying to assign different values at the same time #100, which is resolved to Z.
 

you assign input values after 100 time units, if by chance the default
simulation time is the same or shorter you will get the results described;
change:
initial begin
#100
a = 2'b01;
index = 1'b0;
to
initial begin
a = 2'b01;
index = 1'b0;
---
have fun
 

j_andr said:
you assign input values after 100 time units, if by chance the default
simulation time is the same or shorter you will get the results described;
change:
initial begin
#100
a = 2'b01;
index = 1'b0;
to
initial begin
a = 2'b01;
index = 1'b0;
---
have fun
Click to expand...

i m using `timescale 1ns / 1ps and simulation is running for 1000ns = 1µs.

so that removing #100 from the start did not work!!

what else could be wrong.. this simple thing is driving me crazy :evil:

Saad
 

I run your example in Questasim and as expected first 100ns are red 'Xs'
then looks ok, I'm afraid I can't help more;
----
 

HTML: 
module test_single_bit;

	reg [1:0] a;
	reg index;
             wire out;

	single_bit uut (
		.a(a), 
		.out(out), 
		.index(index));

	initial begin
		#100
		a = 2'b01;
		index = 1'b0;
		
		#100
		index = 1'b1;
		end      
endmodule

Remove the semicolon, you will see expected results in ISIM
 

dcreddy1980 said:
Remove the semicolon, you will see expected results in ISIM
Click to expand...

which semicolon?? I removed all of them in the stimulus but its behaving the same way.. :-(
 
Last edited:

module test_single_bit;

reg [1:0] a;
reg index;
wire out;

single_bit uut (
.a(a),
.out(out),
.index(index));

initial begin
#100
a = 2'b01;
index = 1'b0;

#100
index = 1'b1;
end
endmodule

The above code works for me in ISIM. Its suprising why you are seeing Hi-Z on the inputs.
 

dcreddy1980 said:
The above code works for me in ISIM. Its suprising why you are seeing Hi-Z on the inputs.
Click to expand...

I dont know whats wrong. I have previously used modelsim. Are there any simulation/project settings specific to ISIM, which might be causing problems for me?
 

when in doubt, rebuild the project.
 
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    saad

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