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[SOLVED] VHDL Error Multiple declarations of "+" included via multiple use clauses"

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blooz

blooz

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VHDL Error Multiple declarations of "+" included via multiple use clauses"

The Exact Error is reported as ...

line 43.Multiple declarations of "+" included via multiple use clauses; none are made directly visible

particular Line is

G <= A + B + UNIT;
 

Re: VHDL Error Multiple declarations of "+" included via multiple use clauses"

I guess you are trying to add signed or unsigned types and you included both numeric_std and std_logic_arith. Both files declare a signed and unsigned type and the arithmetic functions for them. Because of this, it doesnt know which one to use, so wont let you use either without specifiying which ones:

signal a : numeric_std.unsigned(7 downto 0);
signal b : numeric_std.unsigned(7 downto 0);
signa g : numeric_std.unsigned(7 downto 0);

g <= a numeric_std.+ b;

I would stick with just numeric_std because it is a real standard, std_logic_arith is not.
 
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