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Help with OC PCI BRidge core...

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Sink0

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Hi, i am trying to ake use of OC Pci Bridge on my designe, and finally i could make it work as i want. I can master the network and receive/send bursts of data on Linux. But i need a sugestion now. I need to transfer some data to computer, and to tell it when the transfer is done i will generate a interrupt. My question is.. when i finish transfer data from my wishbone master to the slave at the bridge, it does not mean that all the data was transfered to the computer.. so how can i know when all the data is at the computer's memory, so i can generate the interrupt?

Thank you, let me know if i was not enough clear.
 

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