jlon
Newbie level 4
Using Libero's SmartGen tool, today I created a 16-bit Brent-Kung adder/subtractor. I pasted the resulting Verilog code into an ALU module and ran a few (10) tests against it. It ran fine. And the result was a LOT smaller than the one synthesized from pure behavioral Verilog.
But when I synthesized it with Synplify, the synthesis report showed that it removed numerous AND2 gates: "CL 168 Pruning instance AND2_xx -- not in use..." :-?
How can this be? I'd expect that a generated structural-modeled module like this would have only what is needed. Should I be worried?
But when I synthesized it with Synplify, the synthesis report showed that it removed numerous AND2 gates: "CL 168 Pruning instance AND2_xx -- not in use..." :-?
How can this be? I'd expect that a generated structural-modeled module like this would have only what is needed. Should I be worried?