Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

synthesis problem about (variable and constant)

Status
Not open for further replies.

hodahussein

Full Member level 2
Joined
Apr 17, 2007
Messages
144
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
2,276
dear all

about constant and variables
are they synthesized or not?
if i assume constant : integer :=123;
what is the representation of this number in RTL schematic?

also about signal declaration
if i assume that
signal x :integer := 124;
is it right or not؟
after synthesis processing what is representation in RTL schematic?

wait your reply for importance
regards
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top