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combinational vs sequential

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hossam abdo

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if i have a circuit block , and i want to write VHDL code to describe it
i can write the code in either concurent statements or sequential statements.

but from the synthesis view , which of them is better.

thanks in advance
 

They are the same, no difference. Normally from coding point of view, if the logic is big or complex, you want to use sequential statements. Otherwise, if it relatively simple, use concurrent.
 
please , also i want to know . the eeprom standard cell in TSMC (its work and IO) , and the tool to generate the memory(eeprom)
 

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