mixing clocks in a scan chain

Hi,

I am a bit confused about how scan works in ASIC designs, especially when we mix clocks in the same chain. On searching this forum, I found the following answer from a post on similar topic: https://www.edaboard.com/threads/199460/

You can mix the clocks on the same chain.
For shifting, having lockup latches can give you a solution to avoid metastability issue.
For capturing, you just can't toggle all the clocks at once. You need to toggle one clock at a time and all works fine.

However, it is still not very clear to me. I have the following questions.

(1) Firstly, here are we talking about the same clock being used in scan shift and scan capture modes?
(2) If we do mix clocks in a scan chain, can the clocks be of any frequency or is there any restriction on that? I am not very clear on how scan shift will work with clocks of two different frequencies even if we insert lockup latches. If the clock used at the beginning of the chain has greater frequency and data is scanned in using that clock, then the flop-flops on the other clock will miss data during shift, correct?
(3) Why can we not toggle all the clocks in the chain during scan capture? What is the problem with that?

Also, if anyone can point me to some source explaining clock mixing in scan chain in greater detail (preferably with some diagrams and examples), that will be great.

Thank you.

1. yes.
2. No you can't. There is a restriction in clock speed. First, all the shift clock must be at the same speed, second, some clock frequencies don't work.
3. if you want to toggle all the capture clocks, you have to balance the clock insertion delay of all the clock tree. Too much effort.

Thanks for your reply, but I do not understand some of your answers very clearly.

lostinxlation said:

2. No you can't. There is a restriction and that's the point of a lock up latch.

Click to expand...

What is the restriction? Do they have to be synchronous or same frequency?

lostinxlation said:

3. if you want to toggle all the capture clocks, you have to balance the clock insertion delay of all the clock tree. Too much effort.

Click to expand...

But what if there is a capture/functional path between two flops with different clocks in the same chain? If we are not toggling both clocks, then we will not be able to capture the data from the first flop to the second one, right?

Thanks.

supersonic_528 said:

What is the restriction? Do they have to be synchronous or same frequency?

Click to expand...

They are synchronous and at the same clock frequency.
The path crossing the clock domain may have hold viols since the clock insertion delay of the two clocks could be arbitrary. A lock up latch makes the domain crossing path a half cycle path, and a hold violation on a half cycle path can be avoided by changing the clock frequency. Therefore, some clock frequencies can not work.THat's the whole point of a lock up latch.

But what if there is a capture/functional path between two flops with different clocks in the same chain? If we are not toggling both clocks, then we will not be able to capture the data from the first flop to the second one, right?

Thanks.

Click to expand...

One clock domain at a time. You toggle one of the clocks and the path to the first flop is tested. Then you toggle another clock to test the second flop.

lostinxlation said:

One clock domain at a time. You toggle one of the clocks and the path to the first flop is tested. Then you toggle another clock to test the second flop.

Click to expand...

So basically if there is a capture path between FF1 (using clk1) and FF2 (using clk2), for capture cycle we are just toggling clk1 and not clk2. This is to avoid any timing issue on the path FF1/Q to FF2/D, correct? But are we not verifying timing on the same path already for functional mode? So if we know that the same path has no timing problem in functional mode, why are we trying to avoid it during scan capture cycle?

Thanks.

if you know there is no timing issue on the path, you can toggle both clock. But you don't want to spend a lot of time to check the timing that is just for test and has alternative solution. Time to market is important.

assuming that their are two clock domains (clk1 and clk2) separated by a lock up latch, don't you also have the restriction that the rising edge of clk2(later domain in scan chain) must not violate setup and hold of the Latch output signal?

To be clear, you cannot pass a signal from one clock domain to another with a simple latch unless you KNOW the relationship (skew) of the clocks. You will be subject to setup and hold violations. Can someone shed some light on this very simple topic?

The lock up latch can easily sample the shifted data from clk1 domain by inverting clk1 and using it as the latch clock. Assuming clk2 can be out of phase with clk1 by any degree, then you have accomplished nothing with a lock up latch. The rising edge of clk2 may be coincident with the changing output value of the latch, Someone please educate me. Thanks.

tdminion said:

The lock up latch can easily sample the shifted data from clk1 domain by inverting clk1 and using it as the latch clock. Assuming clk2 can be out of phase with clk1 by any degree, then you have accomplished nothing with a lock up latch. The rising edge of clk2 may be coincident with the changing output value of the latch, Someone please educate me. Thanks.

Click to expand...

Change the clock speed. That's the whole point of a lockup latch.

This is a relatively novice question (i.e. I'm a novice at running DFT tools), but a chip could have quite a few lock-up latches. How would you go about determining a single "shift clock frequency" that works for all scan chains? It doesn't seem pausible that you would just 'change' the clock frequency until you find one that produces the correct results across all scan chains. Thanks.

Go with a VERY slow frequency and you are very unlikely to have metastability issue with lockup latches.

Thank you 'lostinxlation.' If the latency of all clock trees is less than 1/2 a "shift clock cycle", then there is no chance of metastability. I don't fully understand the clocking waveforms for scan shift and capture with respect to "At Speed" tests and how the lock-up latch will work in this scenario, but I'll save that question for later. Regards.