Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Constraint extraction in design compiler

Status
Not open for further replies.
X

xman24

Junior Member level 2
Joined
Oct 10, 2010
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,444
Hi..
I have constrained my top module which contains some 5 major blocks... I need to extract the block level constraint from this..How and what is the command to extract the block level constraints from top module constraints so that I can do block level synthesis using that..
Please Reply asap...
Thank You
 

I guess 'write_sdc" should work for you. Please note that I've never worked on Design Compiler. I studied somewhere, so please check it.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top