Single cycle Mips processor

plz any one help to modify the MIPS single cycle processor for lui and shift instructions. or any one have any link related to that.

unless you tell us what part of that you don't understand, we cannot help. You can find the instruction description in any MIPS architecture manual.

can you plz tell me that the architecture mention in the link that i post below is applicable for all instruction sets in MIPS. SUCH AS
• Add , addi , sub , mul , lw , sw , sb , lh , lb , sh , lui , and , or , nor , xor , andi , ori , xori, sll , srl , slt , slti , beq , bne, bgtz ,blez ,bltz , j , jr , jal

processor.png (image)

Plz anyone who tell me.... about my above Question??

When i wrote instructions of sll and slr in instruction memory then i get an error of illigall digit here the code of instruction memeory. at the end of this code there is the code of sll in which i have problem so please anyone check it out and tell me the actual problem .


//Instruction_Memory
module Instruction_Memory(address, out);
input [31:0] address;
output [31:0] out;
reg [7:0] mem [255:0];
initial
begin
///////////////////////////////////////////////////////////////////////
// Type
// MIPS assembly
// Meaning
// Binary Conversion
// Hex Conversion
///////////////////////////////////////////////////////////////////////
// r-format addition
// add r2,r0,r1
// rf[2] = rf[0] + rf[1]
// 000000_00000_00001_00010_00000_100000
// 00011020
mem[0] = 8'h00;
mem[1] = 8'h01;
mem[2] = 8'h10;
mem[3] = 8'h20;
// r-format subtraction
// sub r2,r4,r2
// rf[2] = rf[4] - rf[2]
// 000000_00100_00010_00010_00000_100010
// 00821022
mem[4] = 8'h00;
mem[5] = 8'h82;
mem[6] = 8'h10;
mem[7] = 8'h22;
// r-format addition -----> accumulation
// add r2,r2,r4
// rf[2] = rf[2] + rf[4]
// 000000_00010_00100_00010_00000_100000
// 00441020
mem[8] = 8'h00;
mem[9] = 8'h44;
mem[10] = 8'h10;
mem[11] = 8'h20;
mem[12] = 8'h00;
mem[13] = 8'h44;
mem[14] = 8'h10;
mem[15] = 8'h20;
mem[16] = 8'h00;
mem[17] = 8'h44;
mem[18] = 8'h10;
mem[19] = 8'h20;
mem[20] = 8'h00;
mem[21] = 8'h44;
mem[22] = 8'h10;
mem[23] = 8'h20;
// store word ------> no offset
// sw r0,0(r1)
// data_mem[rf[1] + 0] = rf[0]
// 101011_00001_00000_0000000000000000
// AC200000
mem[24] = 8'hAC;
mem[25] = 8'h20;
mem[26] = 8'h00;
mem[27] = 8'h00;
//store word ------> with offset
// sw r2,65(r1)
// data_mem[rf[1] + 65] = rf[2]
// 101011_00001_00010_0000000001000001
// AC220041
mem[28] = 8'hAC;
mem[29] = 8'h22;
mem[30] = 8'h00;
mem[31] = 8'h41;
//load word ------> with offest
// lw r4,65(r1)
// rf[4] = data_mem[rf[1] + 65]
// 100011_00001_00100_0000000001000001
// 8C240041
mem[32] = 8'h8C;
mem[33] = 8'h24;
mem[34] = 8'h00;
mem[35] = 8'h41;
// be -----> does not jump
// beq r0,r1,16
//as rf[0] != rf[1] so it will not jump, see PC which will be PC = PC+1
// 000100_00000_10000_0000000000000100
// 10100004
mem[36] = 8'h10;
mem[37] = 8'h10;
mem[38] = 8'h00;
mem[39] = 8'h04;
// be -----> jumps
// beq r0, r0,16
// as rf[0] == rf[0] so it will jump to PC = (PC + 4) + 16
// 000100_00000_00000_0000000000000100
// 10000004
mem[40] = 8'h10;
mem[41] = 8'h00;
mem[42] = 8'h00;
mem[43] = 8'h04;
// jump
// j 0
// jump to location '0' observe PC which is zero here
// 000010_00000000000000000000000000
// 08000000
mem[60] = 8'h08;
mem[61] = 8'h00;
mem[62] = 8'h00;
mem[63] = 8'h00;

// sll $r1, $ r2,2
//00020880 hex form
mem[64] = 8'bh00;
mem[65] = 8'bh02;
mem[66] = 8'bh08;
mem[67] = 8'bh80;
end
assign out = {mem[address] , mem[address + 1],
mem[address + 2], mem[address + 3]};
endmodule

ss_engg said:

// sll $r1, $ r2,2
//00020880 hex form
mem[64] = 8'bh00;
mem[65] = 8'bh02;
mem[66] = 8'bh08;
mem[67] = 8'bh80;

Click to expand...

..........

whats the issue in it? can you please tell me??

Well ss_engg,

It would be prudent of you to take a few minutes, take a deep breath, carefully examine the snippet of code that lostinxlation has so graciously displayed for you and pay particularly close attention to the way it it has been presented.

And if you still can't see the problem, compare the snippet with a similar section of your code that doesn't throw a compiler error.

just some lines above ...

i try to observe it carefully but when i run that code of shift logic left (written in last)in instruction memory module the xilinx show error when we click to check the syntax.

---------- Post added at 18:32 ---------- Previous post was at 18:29 ----------

i need another suggestion about the final year project. plz tell me any site to search it for Electrical engineering of bachelor level..

ss_engg said:

i try to observe it carefully but when i run that code of shift logic left (written in last)in instruction memory module the xilinx show error when we click to check the syntax.

Click to expand...

The error message you receive is due to a syntax error and lostinxlation has pointed it out to you by BOLDING the syntactical error in the code snippet!

Fix the syntactical error and recompile.

Ciao

Thank you very much. I found that.. can you please suggest any site related to final year projects of electrical Engineering for graduate level.

What area of Electrical Engineering? Control, Communication, Power, etc?

about control and power..

well have you any idea???