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arithmetic shift and latches in vhdl

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alkaios

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hello :)

I want to ask: does shift arithmetic always creates latches in vhdl?
Is there any way to prevent this from happening?
Should I or should I not care about these latches?

Here's my code: 

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
 
entity xReadCounter is
Port    (   clk: in STD_LOGIC;
        rxEnable: in STD_LOGIC_VECTOR (1 downto 0);
        reducEn : in std_logic;
        xrcheck : out std_logic;
        rqoutx: inout STD_LOGIC_VECTOR(12 downto 0));
end xReadCounter;
 
architecture Behavioral of xReadCounter is
 
signal xreduce : std_logic_vector (12 downto 0) := "0000000001000";
 
attribute shreg_extract: string;
attribute shreg_extract of xreduce: signal is "yes"; 
 
begin
 
-----x read counter---------
process(clk)
begin
    if (clk'event and clk = '1') then       
      if rxEnable = "00" then
         rqoutx <= "0000000001000";
        elsif rxEnable = "01" then
            rqoutx <= rqoutx - xreduce;
        elsif rxEnable = "10" then     
            rqoutx <= rqoutx + 1; 
        else
            rqoutx <= rqoutx;
        end if;
    end if;     
end process;
 
process (clk)
begin
    if (clk'event and clk = '1') then
        if reducEn = '1' then
            xreduce <= '0' & xreduce(12 downto 1);
        else
            xreduce <= xreduce;
        end if;
    end if;
end process;
 
xrcheck <= '1' when xreduce = "0000000000001" else '0';
 
end Behavioral;


In the second process, i do the sra in the signal xreduce.
I used the shreg_extract constraint, because i thought it would help.
Is my code correct?

here are the warnings that XST produces:

Code VHDL - [expand]
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=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
WARNING:Xst:1426 - The value init of the FF/Latch xreduce_3 hinder the constant cleaning in the block xReadCounter.
   You should achieve better results by setting this init to 0.
WARNING:Xst:1293 - FF/Latch <xreduce_12> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_11> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_10> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_9> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_8> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_7> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_6> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_5> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_4> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
 
.............................................................................................................................
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch xreduce_3 hinder the constant cleaning in the block xReadCounter.
   You should achieve better results by setting this init to 0.
WARNING:Xst:1293 - FF/Latch <xreduce_12> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_11> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_10> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_9> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_8> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_7> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_6> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_5> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <xreduce_4> has a constant value of 0 in block <xReadCounter>. This FF/Latch will be trimmed during the optimization process.
....................................................................................................................


Thanks in advance
 
Last edited:

Code: 
        if reducEn = '1' then
            xreduce <= '0' & xreduce(12 downto 1);
        else
            xreduce <= xreduce;
        end if;
xreduce starts at 0. on enable, it gets a 0 shifted in. the value can never be anything but 0, so the synthesis tool removes it and replaces it with a constant.
 

permute said:
xreduce starts at 0. on enable, it gets a 0 shifted in. the value can never be anything but 0, so the synthesis tool removes it and replaces it with a constant.
Click to expand...

i don't understand what i do wrong.
i initialize xreduce inside the architecture:

signal xreduce : std_logic_vector (12 downto 0) := "0000000001000";

with a simple testbech, the design looks that it works fine.

Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY xReadCount_tb IS
END xReadCount_tb;
 
ARCHITECTURE behavior OF xReadCount_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT xReadCounter
    PORT(
         clk : IN  std_logic;
         rxEnable : IN  std_logic_vector(1 downto 0);
         reducEn : IN  std_logic;
         xrcheck : OUT  std_logic;
         rqoutx : INOUT  std_logic_vector(12 downto 0)
        );
    END COMPONENT;
    
 
   --Inputs
   signal clk : std_logic := '0';
   signal rxEnable : std_logic_vector(1 downto 0) := (others => '0');
   signal reducEn : std_logic := '0';
 
    --BiDirs
   signal rqoutx : std_logic_vector(12 downto 0);
 
    --Outputs
   signal xrcheck : std_logic;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: xReadCounter PORT MAP (
          clk => clk,
          rxEnable => rxEnable,
          reducEn => reducEn,
          xrcheck => xrcheck,
          rqoutx => rqoutx
        );
 
   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for 50us;
        clk <= '1';
        wait for 50us;
   end process; 
 
   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 150us;   
        rxEnable <= "00";
      wait for 150us;
        rxEnable <= "10";
        wait for 150us;
        rxEnable <= "00";
        reducEn <= '1';
        wait for 50us;
        reducEn <= '0';
        wait for 150us;
        rxEnable <= "10";
        wait for 150us;
        rxEnable <= "01";
      wait for 250us;
        rxEnable <= "11";
        reducEn <= '1';
        wait for 150us;
        reducEn <= '0';
        rxEnable <= "01";
        wait for 150us;
        rxEnable <= "11";
      wait;
   end process;
END;


33_1301835375.jpg


is there anything that i could do to prevent these latches from being created after synthesize, or should i ignore them???
 
Last edited:

oh, i missed that. it only removed bits 12 to 4, and not the 3 you used.

and the warning is that something is being replaced by a constant value, not that you have latches. It simply states that the element is either a register or a latch.
 
permute said:
oh, i missed that. it only removed bits 12 to 4, and not the 3 you used.

and the warning is that something is being replaced by a constant value, not that you have latches. It simply states that the element is either a register or a latch.
Click to expand...


thank you! finally i understand this message!

so, in other words, there is nothing different that i can do with my code and my design won't have problems because of that. right?
 

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