+ Post New Thread
Results 1 to 5 of 5
  1. #1
    Newbie level 2
    Points: 410, Level: 4

    Join Date
    Sep 2010
    Posts
    2
    Helped
    0 / 0
    Points
    410
    Level
    4

    cadance error in designing the layout of Flipped Voltage Follower

    I am using Cadence for the designing an flipped voltage follower.
    I'm a bit stuck understanding what these error messages mean in the DRC checker.
    if there is a link where I can find an explanation please let me know, otherwise I'd really appreciate some help understanding the following:

    1. Welnotr_StampErrorFloat
    (NWEL is highlighted)

    2. 4:16n Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
    all nmos diffusion highlighted

    3. 4:17N Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
    all pmos diffusion highlighted
    please reply me...
    please...



    thanks

    •   AltAdvertisement

        
       

  2. #2
    Full Member level 4
    Points: 2,385, Level: 11

    Join Date
    Jun 2010
    Location
    Bangalore
    Posts
    237
    Helped
    82 / 82
    Points
    2,385
    Level
    11

    Re: cadance error in designing the layout of Flipped Voltage Follower

    check if theres P+ N+ overlap....



    •   AltAdvertisement

        
       

  3. #3
    Newbie level 4
    Points: 389, Level: 4

    Join Date
    Dec 2010
    Posts
    7
    Helped
    1 / 1
    Points
    389
    Level
    4

    Re: cadance error in designing the layout of Flipped Voltage Follower

    Perhaps N+/P+ implant layers overlaped.



    •   AltAdvertisement

        
       

  4. #4
    Super Moderator
    Points: 51,806, Level: 55
    Achievements:
    7 years registered
    erikl's Avatar
    Join Date
    Sep 2008
    Location
    Germany
    Posts
    8,085
    Helped
    2660 / 2660
    Points
    51,806
    Level
    55

    Re: cadance error in designing the layout of Flipped Voltage Follower

    You need P+ substrate taps ("pick ups") closer than 20µm to every well.



  5. #5
    Advanced Member level 1
    Points: 4,010, Level: 14
    Achievements:
    7 years registered

    Join Date
    Jul 2009
    Location
    USA
    Posts
    425
    Helped
    160 / 160
    Points
    4,010
    Level
    14

    Re: cadance error in designing the layout of Flipped Voltage Follower

    Quote Originally Posted by neeraj yadav View Post
    I am using Cadence for the designing an flipped voltage follower.
    I'm a bit stuck understanding what these error messages mean in the DRC checker.
    if there is a link where I can find an explanation please let me know, otherwise I'd really appreciate some help understanding the following:

    1. Welnotr_StampErrorFloat
    (NWEL is highlighted)

    2. 4:16n Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
    all nmos diffusion highlighted

    3. 4:17N Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
    all pmos diffusion highlighted
    please reply me...
    please...



    thanks
    it looks like you do not have body ties in your layout, you need n+ to high voltage (higher than or equal to any PFET source terminals in that well) in Nwells and p+ to low voltage (lower than or equal to the source of all NFETs in that well) in Pwells

    If this is an analog layout you should have a body tie close to all FETs



--[[ ]]--