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Resistor Mismatch Simulation

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themaccabee

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Hi ,
I need to do a simulation showing that the resistors in the second stage of a 3 opamp instrumentation amplifier greatly affect the CMRR while the resistors in the first stage doesnt.

As per some suggestions im looking onto Monte carlo analysis..Im hoping that its the right way to do it.

I ve done a simulation with 10K, 1% tolerance & 10% lot tolerance for resistors in second stage for this circuit and i got a histogram output from pspice 9.1..

Now
1)I dont understand the Histogram completely..(the Y axis is in Volts)
2)Shall i take the mean output voltage and use it to calculate the worst case CMRR?
3)Then i should do a similar analysis with first stage resistors and calulate the worst case CMRR in a similar way?

 

The mean of the histogram (x-axis) should be close to the value for the ideal resistors. The standard deviation tells you how much the resistor mismatch affects your circuit. In your case, you need to compare the standard deviations of the different stages to determine which one affects your circuit the most.
 
So can i take the maximum value indicated in the histogram as the worst case output voltage for a particular simulation case???
Thanks
 

I don't know, it depends on your application. In some cases the maximum value is the worst case, in some other cases it is the minimum value...
 
It might be the worst case for the given assumptions, but
the real trick is in assigning realistic variation to all of the
components that matter. Your histogram would give you
an upper / lower bound. But you also need to work from
sample size (number of MC iterations) to confidence level
and however many sigma you want to express limits as.
 
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