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program not running on fpga board

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vani_pat

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Hi All,

I have written vhdl code for input clock freq scaling from 32 MHz down to 8 MHz as follows:

library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;


ENTITY timeInterval_reg IS
GENERIC(REGWIDTH : integer := 2);
PORT( clk_out : OUT std_logic;
----This factor is equal to 125ns/31.25ns = 4 to achieve 8 MHz(125ns)--------
clk_period : IN std_logic_vector(REGWIDTH-1 downto 0):= "11";
en : IN std_logic:= '1';
clk : IN std_logic);
rst_n : IN std_logic;

end entity timeInterval_reg;

architecture rtl of timeInterval_reg is

signal wrap : std_logic:= '0';
signal count : std_logic_vector(REGWIDTH-1 downto 0):= (OTHERS => '0');

begin

process (clk, en, wrap)
begin
if (rst_n = '0') then
count <= '0';
wrap <= '0';
if rising_edge(clk) then
if (en = '1') then
if (count = clk_period) then
wrap<='1';
count <= (OTHERS => '0');
else
wrap <= '0';
count <= count+1;
end if;
else
wrap <= '0';
end if;
end if;
end if;
end if;

end process;
clk_out <= wrap;

end rtl;


I have tested it on the ISIM using test bench it works fine, but as I programmed it to my fpga board and checked through scope no response has been displayed corresponding to clk_out signal, it shows zero signal. I am using Papilio one fpga board and has set proper pin connections to ucf file. Is my code is logically correct?? or I am missing any requirement needed.

Thanx in advance!!!
 

Hi,

You have some issues in your process.

Firstly, in the sensitivity list you have to add the asynch reset "rst_n" you also have to remove "en" and "wrap" signals from the list then for clock event you should use "elsif" instead of "if" in order that the synthesizer infers FFs.

With these changes your process will look like :

Code: 
process (clk, rst_n)
begin

  if (rst_n = '0') then
    count <= '0';
    wrap <= '0';
  elsif rising_edge(clk) then
    if (en = '1') then
      if (count = clk_period) then
        wrap <='1';
        count <= (OTHERS => '0');
      else
        wrap <= '0';
        count <= count+1;
      end if;
    else
      wrap <= '0';
    end if;
  end if;
  
end process;

You have also a typo in the entity, you should move the bracket after rst_n input.


Yours,
 

I don't think this can be synthesized because you have errors, so i can't understand how did you test it with ISIM

Code: 
ENTITY timeInterval_reg IS
GENERIC(REGWIDTH : integer := 2);
PORT( clk_out : OUT std_logic;
----This factor is equal to 125ns/31.25ns = 4 to achieve 8 MHz(125ns)--------
clk_period : IN std_logic_vector(REGWIDTH-1 downto 0):= "11";
en : IN std_logic:= '1';
clk : IN std_logic);
rst_n : IN std_logic;

end entity timeInterval_reg;

architecture rtl of timeInterval_reg is

signal wrap : std_logic:= '0';
signal count : std_logic_vector(REGWIDTH-1 downto 0):= (OTHERS => '0');

begin

process (clk, en, wrap)
begin
	if (rst_n = '0') then
		[COLOR="red"][B]count <= '0';[/B][/COLOR]  -- count is a vector so this is wrong
		wrap <= '0';
		if rising_edge(clk) then
			if (en = '1') then
				if (count = clk_period) then
					wrap<='1';
					count <= (OTHERS => '0');
				else
					wrap <= '0';
					count <= count+1;
				end if;
			else
				wrap <= '0';
			end if;
		end if;
	end if;
[COLOR="red"][B]end if;[/B][/COLOR]  -- there is no if left to close

end process;
clk_out <= wrap;

end rtl;

Alex
 

With the following code the synthesize will pass :

Code: 
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;


ENTITY timeInterval_reg IS
GENERIC(REGWIDTH : integer := 2);
PORT( clk_out : OUT std_logic;
----This factor is equal to 125ns/31.25ns = 4 to achieve 8 MHz(125ns)--------
clk_period : IN std_logic_vector(REGWIDTH-1 downto 0):= "11";
en : IN std_logic:= '1';
clk : IN std_logic;
rst_n : IN std_logic);

end entity timeInterval_reg;

architecture rtl of timeInterval_reg is

signal wrap : std_logic:= '0';
signal count : std_logic_vector(REGWIDTH-1 downto 0):= (OTHERS => '0');

begin

process (clk, rst_n)
begin

  if (rst_n = '0') then
    count <= (others => '0');
    wrap <= '0';
  elsif rising_edge(clk) then
    if (en = '1') then
      if (count = clk_period) then
        wrap <='1';
        count <= (OTHERS => '0');
      else
        wrap <= '0';
        count <= count+1;
      end if;
    else
      wrap <= '0';
    end if;
  end if;
  
end process;

clk_out <= wrap;

end rtl;
 

Thanx for all your replies........

this was not the exact code that i have tested on ISIM...i have corrected the things already and then tested...sorry for mistype...nyways...it still not works as expected....I have no clue where is the mistake??

Looking for ur suggestions...

Thanx..
 

I don't think you need to set count <= (OTHERS => '0'); because it is a 2bit vector , after 11 it will go to 00 anyway.
Also you can use a different way, instead of count and wrap you can use a 3bit count and use the MSB as clock output

000
001
010
011
100
101
110
111
000

use clk_out <= count(2); insted of clk_out <= wrap;

Alex

---------- Post added at 13:15 ---------- Previous post was at 13:05 ----------

What i do is divide by 8 actually, you should use a 2bit count and
use clk_out <= count(1);

00
01
10
11
00
01
10
11

This way you will also have a symmetric clock wave.
if you want it as before (positive clock pulse duration same as original clock) you can use clk_out <= (count(1) and count(0));

Alex
 

Thanx for all ur replies....My code is working now with desired output...
@alex:Thanx Alex for the another way too...
 

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