[SOLVED] readmemh in verilog and xilinx

ive used the following statement in verilog but im not able to synthesize using xilinx ise 11

$readmemh("water.txt",mem_RGB);

the error messeage is as follows

Value 184321292 found at line 1 is not hexadecimal in call of system task $readmemh.


pls help..


thank you.

$readmemh is not synthesizeable. It is used for simulation or behavioural code only.

r.b.

what other option can i use??

If you are intializing a memory, you can specify a .coe file when you generate the memory core and the memory. Once implemented, will power up with the values in the .coe file. Refer to Xilinx documentation for information on how to do that.

for FPGAs, readmemh is synthesizable. Xilinx has slightly better support than Altera. Xilinx allows any generic/constant/literal to be used for a filename, while Altera only allows hard-coded literals. But both XST and quartus support readmem.

readmemh is simply placed in an initial begin-end block.

I suspect the issue is the invalid data width or such. I don't know the declaration of mem_RGB, nor the first line of "water.txt"

this is apart of of my code.

reg [8:0] mem_RGB [0:767];
wire[8:0] mem_Y [0:255];
reg [8:0] mem_WATERMARKED [0:255];
initial
begin
$readmemh("water.txt",mem_RGB);
end

ive attached the water.txt file


View attachment water.txt

Again initial statement is not synthesisable so is readmemh.

Use BlockRAM for initialization.

Jack// ani said:

Again initial statement is not synthesisable so is readmemh.

Use BlockRAM for initialization.

Click to expand...

No, it works. I've used it several times. Both Xilinx and Altera provide documentation that shows how to use it.

@prat:
water.txt is not in the correct format. readmemh expects 1 datapoint per line. you have all of the datapoints on the same line.

permute said:

No, it works. I've used it several times. Both Xilinx and Altera provide documentation that shows how to use it.

Click to expand...

Good to know, it will make things easy! Can you please post links to those documentation?

it is in the sections about inferring block rams. Also, Altera's tools are a bit dangerous in that in some cases they will fail silently. Eg, some use cases of inferred block ram will not use the readmemh line, but will not show any info/warning/error. Ironically, it becomes easier to mis-size (widths or depth) the entries in the readmem file as these conditions are warnings and will show that the RAM is initialized in synthesis.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/xst_v6s6.pdf
This is described in the XST (13.1, v6s6) user manual on pages 86 and 221. The Quartus manual also shows how to use readmem. Just be sure to read the sections about all of the HDL issues with inferring specific hardware features, as they can be device dependent or non-obvious or benefit from additional synthesizer attributes. For example, many of Xilinx's non-slice registers only have synchronous resets, if any reset at all. Likewise, RAMs may need to register the address, but might not provide that registered signal back into fabric.

If you want to see something really interesting, look at the example of a true dual port inferred block ram starting on page 188 -- it uses VHDL's "shared variables".

@permute::Thanks a ton... my synthesis is successful