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help!!! A question about 12bit SAR ADC THD problem

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pz5921087

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As you can see the structure, it's a 8it SAR ADC, we just replace the capacitor array with split capacitor array to realize a 12bit 1K sampling rate SAR ADC. Its designed for EEG singal processing which has very low frequency.

Now we have builted an ideal model in cadence and use ideal DAC to convert the ADC output. We measured the THD by calculator that shows only -63dB. But it supposed to have a -74dB THD theoretically. Actually we also test the transient result and found that all the sample and hold values are correct and accurate. but why the THD is not sufficient? Is my measurment method of THD wrong? Can anybody explain? Thx!
This problem made me almost crazy.... The deadline for this project is approaching
 

anybody can help me?? Now I am wondering whether my measurement method is right or not. I use the THD function in calculator and directly calculated the output from the ideal DAC. Today I also check the values got from DAC and compare it with the corresponding original signal value. The difference is less than 1LSB, but why the THD result is so small? I am confused
 

hi,pz5921087:
I simulated the THD of codec DAC in cadence before,and used the calculator provided by cadence. I confused by the THD results also, I quitely doubt the reliability of the simuation results of THD. Because the THD results of calculator and of a cell from analoglib is not the same. And when the subject is one cycle is different from two, or three cycles. Maybe you check the arithmetic of THD.
 
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