I have designed a decimator filter for a 8 bit sigma-delta ad convertor. I use one CIC, one halfband and one FIR filter. The output of the decimator is 38 bits. In order to achieve lower power consumption I dont want to cut all 30 LSB bits at the end. Instead of this I want to reduce the output for each stage. For example cutting 5 bits at the output of the CIC, cutting 15 bits at the outputs of the adders in halfband and cutting 18 bits at the outputs of the adders in FIR. And of course there is much error when compared to cutting all 30 bits at the end. I'm confused about the accepted error rate. I'm comparing the output with cutting 30 LSB at the end and cutting bits for each stage. Please help me about what percentage of error is accepted or give me some idea about the error.