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How to compile and perform simulation on System verilog with DPI-C call using VCS?

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no_mad

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Hi all,

I'm new to SV+DPI-C environment.
I'm using VCS for simulation.

Question 1:
What are the options in VCS to compile C-code together with SystemVerilog codes.

Please shed some light.

Thanks in advance
 

Hi,

I know it's very old post and not sure if I will receive any response. However, I want to give a try.

Can you please post the solution which you had for this problem?
It will be helpful for the person like me who is also in the same situation. I am first time using SV+DPI-C and not sure about VCS command to simulate a test.

Please help if you remember.

Thanks,
Nilesh


no_mad said:
Hi all,

I'm new to SV+DPI-C environment.
I'm using VCS for simulation.

Question 1:
What are the options in VCS to compile C-code together with SystemVerilog codes.

Please shed some light.

Thanks in advance
Click to expand...
 

Hi Nilesh,

Good to hear that you are also doing this :)

Anyway, here how I does it:

1) First u need to generate your *.so file:
>> Example: g++ -Wall -m64 -g -fPIC your_cpp1.cpp your_cpp2.cpp -shared -o your_gen.so


2) VCS compile:
>> Example: vcs -debug_all -full64 -sverilog -R +define+your_define rtl_file.sv your_gen.so

All this you can added into your Makefile and do automation :-D

Hope it helps.

-no_mad
 

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