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simulation results are wrong.

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drba

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Hi,
I am new to this vhdl language.
I am doing structural style of asynchronous(mod 17) counter in vhdl.
I am using xilinx ise .During synthesis no errors were observed.
But in simulation all flip flop outputs are showing 'x;

What might be the wrong thing i am doing.
Help me in this.

Regards,
Drba
 

But in simulation all flip flop outputs are showing 'x
Click to expand...
This is the expected behaviour, if the design misses a suitable initialization of signals respectively a reset.
 
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    drba

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hi,


i applied all the initial conditions .
Its waveforms are like earlier i.e xxxxx.
One funny thing is ,if i put flipflop outputs(q4,q3,q2,q1,q0) as inout signals and initilalize them at port declaration ,everything is working fine.
But the same is not coming if i declare them as signals and then initialize.

why this kind of behavior?

regards,
drba
 

I remember, that missing initialization actually gives "uuu" values while "xxx" refers to incorrect designed logic or timing issues. I previously overlooked the term "asynchronous". Does it mean, you have a counter without a edge sensitive process? This in fact won't be synthesizable.
 
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    blooz

    blooz

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hi,

i am sending my code.
it is getting synthesized and showing results as uuuuu.
i tried by giving initialization value to reset signal s1.
But simulation result is uuuuu.
Earlier because of setting problem it is showing xxxxx[i.e instead of VHDL ,verlog was selected in the properties settings].
i am using ISE9.1.


regards,
drba
 

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  • clock_17.txt
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i got the expected simulation results.Problem is because of uninitialized Reset signal.
your reply is helpful FVM.

Regards,
drba
 

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