acessing a binary string from a test bench input and storing a part of it in an array

the total no. of bits are 112.. so i have to take out the required 8 digit bits from the given 112 bits and store that 8 bits fetched in array..
in which ever way u could do that is acceptable to me..

---------- Post added at 16:59 ---------- Previous post was at 16:58 ----------

can u provide me with complete program with all the syntax's..

Im not here to do your work for you. and the code I posted will do exactly what you want. you select with a and b the bits to extract.

signal my_bits : std_logic_vector(7 downot 0 );

....
my_bits <= sentence(a downto b);

i have made the program is this right ?


entity mywork1 is
Port ( sentence : in STD_LOGIC_vector(111 downto 0);
testut STD_LOGIC_vector);

end mywork1;
architecture Behavioral of mywork1 is

signal arr1 : std_logic_vector(0 to 7);
signal my_bits : std_logic_vector(7 downot 0 );

begin
process(sentence)
my_bits <= sentence(56 downto 49);

end Behavioral;

---------- Post added at 17:19 ---------- Previous post was at 17:18 ----------

i think data will be fetched but there is no means to store it..
can u tell me how to store it in an array ?

type slv_array_t is array(0 to n-1) of std_logic_vector(7 downto 0);
signal storage : slv_array_t;

.....
storage(i) <= my_bits;

where i is the position in the array where you want to store it.

where we have to declare n ? is it necessary to declare ? and i also?

you can just replace it with an integer. or use a generic. Its up to you.

i have written the following program..


entity mywork1 is
Port ( sentence : in STD_LOGIC_vector(111 downto 0));
end mywork1;
architecture Behavioral of mywork1 is
type slv_array_t is array(0 to n-1) of std_logic_vector(7 downto 0);
signal storage : slv_array_t;
signal my_bits : std_logic_vector(7 downto 0 );

begin
process(sentence)
begin
my_bits <= sentence(56 downto 49);
storage(2) <= my_bits;
end process;
end Behavioral;


following error is coming..
ERROR:HDLParsers:1209 - "C:/Documents and Settings/A.Jain/Desktop/newproject/mywork1.vhd" Line 37. slv_array_t: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Documents and Settings/A.Jain/Desktop/newproject/mywork1.vhd" Line 44. Undefined symbol 'storage'.
ERROR:HDLParsers:1209 - "C:/Documents and Settings/A.Jain/Desktop/newproject/mywork1.vhd" Line 44. storage: Undefined symbol (last report in this block)

you cannot define a type in a port. You have to declare it either in the entity or in a package.

like where i have to declare that part in the test bench can u write more specific code

types have to be declared in the archture definition (where you declare other signals) if you only want it visible in that file, otherwise for multiple files you have to declare it in a package