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acessing a binary string from a test bench input and storing a part of it in an array

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i am still not able 2 get it can u be little more specific..?
 

I cannot help you without understanding what you are trying to do.
From looking at the code, it appears you have a very weak understanding of VHDL and digital design in general. It looks like you are trying to write VHDL as if it were a programming language. VHDL is a hardware description language used for describing hardware. You cannot write code that looks like C.

If you explain what you are trying to do overall, I may be able to help, but without that, I dont know what you need me to tell you.
 

no no.. that simulation is not done by me (it has errors .. i know ..it's not yet in a final stage)... i have 2 just fetch it from there .. pls tell me what i hav 2 write there in the test bench.. and implemented ur program it is giving errors and there is no provision for where the result will be stored..
 

you cannot "fetch" anything from another file. It has to be passed to you via the ports on your entity. So therefore your entity has to be instantiated inside the testbench code.

I already told you what to write to instantiate your entity.
 

ya.. sorry i dont have to fetch the digits from the above mentioned test bench the whole situation is..
ok... here it goes..
actually i have been assigned to fetch the binary values of the sentence --Aux4^are#156#[]#hEM (which with the help of ascii codes are being converted to it's binary form like 011101010... it is not my part of code ) so i have to extract the binary value of #156# which is say after the 17th pos. in the binary form and till 48 th pos. so I HAVE TO EXTRACT THOSE BINARY DIGITS I.E FROM 16-48 AND STORE IN AN ARRAY AND SEE THE BITS WHICH ARE STORED IN THAT ARRAY IN AN SIMULATION WINDOW..

---------- Post added at 15:17 ---------- Previous post was at 15:12 ----------

i was confused there is no need of test bench in this ... i just have to fetch those values from that binary converted string and display the result in the simulation window..
 

Its still not clear if these ascii values are in a text file or just in the VHDL code. There are no ascii codes in VHDL, just character types (in which their position in the type declaration coresponds to the ascii code with VHDL 93.

Or even worse, you have a commented line. You cannot read comments inside the code. If you really really really have to do this, you will have to write a text parser to read in your VHDL file, find the correct part of the file to parse into a character and then create the string.

Basically, it all sound like you have no idea how to use VHDL properly, and with the evidence of the testbench, it looks like other people have no idea too.
 

ya we all are beginers .. doing the college project.. that commented line is actually in use ... but i dont have worry abt that it will be converted into binary (pls. avoid that sentence) i have to just fetch the binary digits from that ... and dipslay it.. that's all ..

---------- Post added at 15:27 ---------- Previous post was at 15:22 ----------

pls.. help if u could provide me with the complete program.. it will be a gr8 gesture.. :)
 

to display, you need to use the textio library:

use std.textio.all;
use ieee.std_logic_textio.all;

inside your process:

Code:
process
  variable output_line : line;
begin

  write(output_line, string'("This is a load of data: ") );
  write(output_line, sentence(64 downto 48) );  --or Hwrite if you want to output hex

  writeline(OUTPUT, output_line);  --OUTPUT is the system console

end process;


---------- Post added at 11:59 ---------- Previous post was at 11:58 ----------

Just so you know - none of this will work on hardware.
 

the data is not in string form but it is binary data..
 

textio can print any standard types to the console
std_logic_textio allows you to print std_logic_vectors to the console

You can use the code I posted
 

pls. can u provide me with the complete program so that i can run it in my simulation window..
i will able to understand it better if u could write it completely..

---------- Post added at 15:39 ---------- Previous post was at 15:35 ----------

error is coming
ERROR:Xst:2588 - Port <test> of top entity <mywork> is not constrainted.

---------- Post added at 15:40 ---------- Previous post was at 15:39 ----------

i have written the complete program like this.....

entity mywork is
Port ( sentence : in STD_LOGIC_vector(111 downto 0);
test:eek:ut STD_LOGIC_vector);
end mywork;

architecture Behavioral of mywork is
signal arr1 : std_logic_vector(0 to 16);
begin

process(sentence)
variable output_line : line;
begin
write(output_line, string'("This is a load of data: ") );
write(output_line, sentence(64 downto 48 ) );
writeline(OUTPUT, output_line);
end process;
end Behavioral;


but error is coming like..
ERROR:Xst:2588 - Port <test> of top entity <mywork> is not constrainted.
 

Here is a demo. Ill let you work the rest out, especially as you're meant to be learning, not ripping code off the internet.:

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;

use std.textio.all;

entity mywork is
end mywork;

architecture Behavioral of mywork is
  
  constant A_BIG_BINARY_ARRAY : std_logic_vector(63 downto 0) := x"1234567890ABCDEF";
  
begin

  process
    variable output_line : line;
  begin

    write(output_line, string'("Here is the number in binary: ") );
    write(output_line, A_BIG_BINARY_ARRAY );  
  
    writeline(OUTPUT, output_line);  --OUTPUT is the system console
    
    write( output_line, string'("Here is the number in hex: ") );
   hwrite(output_line, A_BIG_BINARY_ARRAY );  
  
    writeline(OUTPUT, output_line);  --OUTPUT is the system console
    
    
    wait;
  end process;

end Behavioral;


---------- Post added at 12:14 ---------- Previous post was at 12:11 ----------

The problem you are getting is because you are trying to compile the design. Be warned: with all this code there is NO WAY you can compile it for an FPGA. You can only run it in a simulator. textio is only meant for debugging code while testing it. If you are intending to drive an LCD display screen or simular, you will have to write a controller for that device that has nothing to do with textio - you will have to read the data sheet on how the display works and write a logic design to drive it from the FPGA. I get the feeling this is what you are trying to do, and you cannot acheive it with the code I posted.

I cannot help with the display controller, because I have no idea how it works without a data sheet.
 

in the above program where the binary digits are being fetched..? there is no array declared also..?
and moreover what is x"1234567890ABCDEF"; ? and instead of writing A_BIG_BINARY_ARRAY i have 2 write there the whole binary array...?

---------- Post added at 15:47 ---------- Previous post was at 15:46 ----------

no no i dont have test it in fpga right now for the time being...
 

x"1234" is the hex form of "0001001000110100"

x infront of the quotes denotes that the string is in hexadecimal.

Run the code in a simulator, you'll see the output in hex and binary.
 

i dont understand this complicated stuff ...i dont need any write commands and all those the binary digits are given .. i have to just extract some part of it.. and display that binary extracted digits..
 

this is very basic VHDL stuff, and you need to know it if you want to display anything. If you want to display code on the console you have to use the write commands.
extraction can just be done by taking the range you want from the input, that I posted earlier. you dont need to use any for loops, jsut and extraction:

some_data <= sentence(64 downto 48 );
 

hi !!
i know it's getting bit irritating for u.. pls dont feel anything bad i just wanted to complete this stuff as i am in pressure..

i have written the sentence and it's bibary form below and i will explain all this to u ..
my sentence is..

Aux4^are #156# []#hEM
its binary form is

"10111001010111100110000101110010011001010010001110011100001000110101101101011101001000110110100001000101010011011100001001011110011001110110111101101001011011100110011101011011010111010010110001011011010111010010110001011011010111010010110001011011010111010010110001011011010111010010001101101010010000010011101000000011
001000110101000100100011"

i have to take the binary converted value of the above sentence (highlighted)
and store it in an array..using for loop
please can u provide me with a complte program:roll:
 

what you are asking makes no sense. There is no need for a for loop. As I have already seen, this array is not a string, it is a std_logic_vector. You can simply extract the bits you want with an assignment.

As is clear, you have very little knowledge of what is going on. Furthermore, all the suggestions I have made have been rejected by you. I really dont know what you really want, and I dont think you know either. I suggest you go back and find a good VHDL book and electronic design guide and read up on how both of these work.
 

how to extract the bits.. i need a program for that only..
 

my_bits <= sentence(a downto b);

where a and b are the range of bits you want to extract.
 

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