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[SOLVED] Sense Amplifier and 1-Transistor DRAM Cell

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SeriousTyro

SeriousTyro

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I'm having troubling understanding how the sense amplifier and DRAM Cell works.

25_1299661074.png

I understand how the write works. If you want to write high, you set WL and BL to high which will charge the storage capacitor.
I don't understand how read works. During the time before the capacitor can fully dissipate, you can read BL?
Whats C_BL for?

35_1299661074.png

I can't seem to follow the circuit. I have a scenario where SE is high. Bit Line is high and Y is low but I am unable to follow the circuit.
How does this circuit work when outputting high and low?

Thanks
 

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You turn on word line, which forces M1 to turn on.
If Cs has high, when M1 gets turned on, the bit line stays charged and nothing changes.
If Cs has low, the charges on the bit line redistributed to the capcitance, Cs + C_bl so that the voltage level on the bit line drops which is detected by the sense amp down the bit line.

C_bl is the cap of the bit line and the ratio of Cs and C_bl determins the voltage level on the bit line upon reading 0 out of memory cell.

SE is enable and is on during evaluation period, I guess.
If bit line is high(X=1), Y gets 0, which turns on M4 and ~Y gets 1.
If bit line is low(X=0), ~Y gets 0 which turns on M3 and Y gets 1.
 
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