hi all,

- I'm still working on my Sigma Delta ADC modelling but i still can't model even the 1st order using Cadence i want to see the noise shaping through ( NTF ) and signal shaping through (STF ) in cadence but how to model the SDADC

for example H(z)= (1/z-1) which block should i use for it ? and the quantizer should i just add noise ( as i have seen in some models ) or to put a quantizer block ( comparator ) ? and the input signal should it be sampled before the modulator or not ? and for the sampling should i use a clocked switch ? please help me i got really confused ..... thanks in advance

Regards,
Ibrahim