navarromoral
Junior Member level 1
Hello everyone.
I would like to ask how is it possible to generate the write enable signal for an SRAM during a hi speed write rate.
I mean, I want to sample the analog input signal at 80 MSPS, then store the value from the ADC into SRAM. So how can I generate the write enable signal taking into account that the sampling period is only 12.5 ns?
For example if I want to generate the write enable signal 3 ns after the rising edge of the clock, and maintain it for 7 ns, how can I guarantee that timing? (because the delays of the logic gates are not constant)
Can you suggest any cpld for this? And any good book on the topic?
Thank you very much!!
I would like to ask how is it possible to generate the write enable signal for an SRAM during a hi speed write rate.
I mean, I want to sample the analog input signal at 80 MSPS, then store the value from the ADC into SRAM. So how can I generate the write enable signal taking into account that the sampling period is only 12.5 ns?
For example if I want to generate the write enable signal 3 ns after the rising edge of the clock, and maintain it for 7 ns, how can I guarantee that timing? (because the delays of the logic gates are not constant)
Can you suggest any cpld for this? And any good book on the topic?
Thank you very much!!