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    SRAM timing for digital oscilloscope.

    Hello everyone.

    I would like to ask how is it possible to generate the write enable signal for an SRAM during a hi speed write rate.

    I mean, I want to sample the analog input signal at 80 MSPS, then store the value from the ADC into SRAM. So how can I generate the write enable signal taking into account that the sampling period is only 12.5 ns?

    For example if I want to generate the write enable signal 3 ns after the rising edge of the clock, and maintain it for 7 ns, how can I guarantee that timing? (because the delays of the logic gates are not constant)
    Can you suggest any cpld for this? And any good book on the topic?

    Thank you very much!!

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    Re: SRAM timing for digital oscilloscope.

    The best way is to use a modern FPGA with a PLL, that allows to generate multiple clock signals of programmable phase and duty cycle, e.g. Altera Cyclone III. You also would want to use the fastest available asynchronous SRAMs with e.g. 8 ns cycle time to get some margin for timing variations.


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    Re: SRAM timing for digital oscilloscope.

    Thank you for your response!! (and sorry for the delay)
    I will certainly consider what you said.

    Thank you again!



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    Re: SRAM timing for digital oscilloscope.

    As long as you remember that using the pll to generate the clock for your ADC will potentially degrade your effective number of bits, the you should be fine.
    But looks like you have a clean 80 MHz clock already, and want to use the PLL to generate fpga internal clocks for digital part.


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    Re: SRAM timing for digital oscilloscope.

    Thanks for your reply mrflibble. As you say I am using a clean clock signal for my ADC, generated by an oscillator, but I do not understand why it would degrade the effective number of bits if I used a clock from a PLL.

    Besides this I was wondering if someone knows where I could find info. about sampling at 80MSPS or more, especially the writing to SRAM part.

    Many thanks!



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    Re: SRAM timing for digital oscilloscope.

    If you would use the PLL from the fpga, then this would be adding substantial jitter to your clock. If you would then use that jittery clock as the sampling clock for your ADC then this would have a negative impact on the aperture uncertainty.

    Analog has a couple of good appnotes on that:
    http://www.analog.com/static/importe...755AN501_a.pdf
    http://www.analog.com/static/importe...als/MT-007.pdf


    mmmh, looks like they reworked AN-501. You might also want to take a look at the older one. Here's an archive:

    http://www.noise.physx.u-szeged.hu/D...tureJitter.pdf


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