Spy glass CDC analysis with FIFO based design

Hi ,

I have a design which has many FIFOs in it. I'm running SPY Glass CDC analysis on it. What I found it report is that Spy Glass is not able to detect the FIFO architecture and generates lots of Error / Warnings like "Data hold check:FAILED" Ac_cdc01a. for the wr and rd pointer flops. It also shouts for underflow/ overflow. But my design uses Full/empty signal and based on it it write/read from FIFO. So why SPyGlass is compaining about it?

I tried -enable_fifo switch to get rid of these warnings. But no help with this. Can any one help me here ?

Another question is , in my design some registers will get a value during initial time of booting only after that it is going be static and hence I have used 2 flop sync but spyglass shouts warning that only 2 flop sync used and data hold check fail. How to tell spyglass not to shout for such signals?

Thanks,
VJ

1. use fifo constraint in sgdc file to resolve fifo issue.
2. use quasi_static constraint in sgdc file to define static signals .

Hope it helps

Hi Sakshi,

Thanks for help.

I tried to put enable_fifo and enable_handshake in sgdc file but it didn't worked.
It says unknown command for both options.
it used with out - i.e. just new line of sgdc file enable_fifo
similarly new line for enable_handshake

Can you please show me example of sgdc file for it?
Do you have any idea that SpyGlass writes any assertions for CDC check?

Thanks,
VJ

1. -enable_fifo & enable_handshake options , you need to put in the spyglass command line . These are spyglass command line options not constraints

2. fifo & quasi_static constraint you need to put in the .sgdc file . Please refer to clock-reset.pdf available in SPYGLASS_HOME/docs for more details .