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Interview Question: Verilog Code To Find Duration Of Clock

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spartanthewarrior

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Hi All,

Can anybody help me answering a question.

Note:- Don't as Jitter, Set-Up, Hold Time Values. I need Verilog logic.

How can i find a duration of a given (Clock) using Verilog. There are two cases when

1) Duty Cycle is 50%

2) Duty Cycle is 30%

Please help me it's important
 

It should look something like this:

initial begin
#500; // wait clock to be stable
@(posedge clk) t1 = $time;
@(posedge clk) t2 = $time;
$write ("The period is : %t", t2-t1);
end
 

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