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Why 85 degree phase margin could be UN-stable?

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poorren

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Hello guys,
I'm trying to design a local oscillator using a Z-comm VCO+National's PLL. In the first pass design, due to some calculation mistake, I designed a loop filter which actually lead to a phase margin 85 degree.
There's a ringing on the tuning line of VCO like this.
57_1298692881.jpg


Now, I corrected the loop filter, and design a phase margin of 45 degree. The loop works fine, and the ringing disappeared. I'm very curious why the phase margin of 85 degree could lead to un-stable of loop. Furthermore, why a phase margin of 45 degree will have stable design. I don't analysis the close loop function poles, but I used a classic active loop filter, which is supposed to satisfy the Routh rule.

I am very confused on this. I'd like to hear your ideas. Thanks.
 
Last edited:

poorren said:
Hello guys,
I'm trying to design a local oscillator using a Z-comm VCO+National's PLL. In the first pass design, due to some calculation mistake, I designed a loop filter which actually has a phase margin 85 degree.
..................
Now, I corrected the loop filter, and design a phase margin of 45 degree. The loop works fine, and the ringing disappeared. I'm very curious why the phase margin of 85 degree could lead to un-stable of loop. Furthermore, why a phase margin of 45 degree will have stable design. I don't analysis the close loop function poles, but I used a classic active loop filter, which is supposed to satisfy the Routh rule.
I am very confused on this. I'd like to hear your ideas. Thanks.
Click to expand...

Poorren, there must be something wrong in your calculation/simulation.
Of course, a loop with a PM=85 deg exhibits no instability.
However, you mention that the loop filter has a margin of 85 deg.
Please note, that the margin of the complete loop is the only margin that matters!
Therefore, the question: How did you measure/simulate the margin?
 

LvW said:
Poorren, there must be something wrong in your calculation/simulation.
Of course, a loop with a PM=85 deg exhibits no instability.
However, you mention that the loop filter has a margin of 85 deg.
Please note, that the margin of the complete loop is the only margin that matters!
Therefore, the question: How did you measure/simulate the margin?
Click to expand...


Hello LvW,
If PM=85 is stable design, why I get ringing on tuning line?
Actually, what I meat is the complete loop margin is 85 degree. I used ADS to simulate the complete design(open loop and close loop). And finding the frequency which open loop gain is 0dB, and then I could derive the close loop phase as PM. What's your usually way to simulate or design the loop filter?
In pratical way, I still couldn't find a method to verify the real PM in circuit.
What's your suggestion on this? Thanks for your reply.
 
Last edited:

Statement 1:
Actually, what I meat is the complete loop margin is 85 degree.

Statement 2:
In pratical way, I still couldn't find a method to verify the real PM in circuit.


Question: What is the combined meening of both statements? Do you know the PM of the open loop or not?

Remark:There are circuits that must not be evaluated in the BODE diagram (including PM) but rather with the complete Nyquist criterion. The PM approach applies to loop gain functions only, that cross the 0 dB line and the 0 deg. line, respectively, only once.
 
The time domain response of a feedback circuit doesn't only depend on the phase margin, also the loop gain characteristic near to unity gain frequency plays a role. But it's unlikely to get ringing with 85 degree phase margin normally.

For the present PLL problem, I wonder if the loop characteristic can be easily determined, because nonlinear elements may be involved.
 
Hello,

Are you sure the graph isn't the result of aliasing, external noise, power supply ripple, etc.

Did you also run a transient simulation where the actual frequency is far away from the set frequency (to see the effect of non-linearity).
 
I don't know the components, but the tune voltage seems to
be bumping off the ground reference. What are your supplies,
and the upper / lower bounds of the linear Vtune range at the
VCO? Loop stability criteria for small signal analysis, depend
on the loop being linear. Maybe you are trying to pull frequency
outside the capable range.

It looks like 10kHz is your fundamental, which is a suspiciously
round number. If (say) some element of your loop -were-
railed out, a local clock or supply chop might find its way through
the gain element to the output with no help from (closed loop)
PSRR.

How about you 'scope-poke some other points around
the loop and sanity-check them against component input /
output range expectations? You have the tools. Having
us "ghosts" speculate, is a poor substitute for that.

You might begin with breaking the loop at Vtune, sweep
Vtune manually while watching frequency and seeing
that the output which would drive Vtune, switches at
the frequency target and that the Vtune applied at that
point, is anything close to what you've got on the
'scope now. Either upper, lower bound or the average.
 
LvW said:
Statement 1:
Actually, what I meat is the complete loop margin is 85 degree.

Statement 2:
In pratical way, I still couldn't find a method to verify the real PM in circuit.


Question: What is the combined meening of both statements? Do you know the PM of the open loop or not?


Remark:There are circuits that must not be evaluated in the BODE diagram (including PM) but rather with the complete Nyquist criterion. The PM approach applies to loop gain functions only, that cross the 0 dB line and the 0 deg. line, respectively, only once.
Click to expand...

>>
Hello,
For statement 1, the 85 degree is from the simulation result. Note, I mentioned that I mistakenly calculated the PM at initial design (erroneous PM equation), when I correct that mistake, I re-simulate the initial design with the correct equation, found that the simulated PM is 85 degree. But, I haven't figure out a method to check circuit is working as simulated.

I'm sorry, I still couldn't fully understand your remark. "Remark:There are circuits that must not be evaluated in the BODE diagram (including PM) but rather with the complete Nyquist criterion. " Could you give more details, thanks advance!

I remember my RF circuit teacher once told us there exists circuit which is Routh Stable, has a PM 180.

---------- Post added at 15:10 ---------- Previous post was at 15:06 ----------
FvM said:
The time domain response of a feedback circuit doesn't only depend on the phase margin, also the loop gain characteristic near to unity gain frequency plays a role. But it's unlikely to get ringing with 85 degree phase margin normally.

For the present PLL problem, I wonder if the loop characteristic can be easily determined, because nonlinear elements may be involved.
Click to expand...

I am wondering how to determinate the loop characteristic in real circuit. All I could do now is guess and simulate. I couldn't figure out an easy way to determinate the difference between the REAL circuit and simulation model. what's your suggestion?

---------- Post added at 15:12 ---------- Previous post was at 15:10 ----------
WimRFP said:
Hello,

Are you sure the graph isn't the result of aliasing, external noise, power supply ripple, etc.

Did you also run a transient simulation where the actual frequency is far away from the set frequency (to see the effect of non-linearity).
Click to expand...

No, I haven't tried (and known how) to simulate the transient behavior of the loop. All I did is simulate, and then try it on real PCB circuit.
 

I am wondering how to determinate the loop characteristic in real circuit.
Click to expand...
It can be measured. Operate the PLL with a slow loop filter to keep it locked, inject an AC signal in front of the VCO and observe the output of the PD.
 

dick_freebird said:
I don't know the components, but the tune voltage seems to
be bumping off the ground reference. What are your supplies,
and the upper / lower bounds of the linear Vtune range at the
VCO? Loop stability criteria for small signal analysis, depend
on the loop being linear. Maybe you are trying to pull frequency
outside the capable range.

It looks like 10kHz is your fundamental, which is a suspiciously
round number. If (say) some element of your loop -were-
railed out, a local clock or supply chop might find its way through
the gain element to the output with no help from (closed loop)
PSRR.

How about you 'scope-poke some other points around
the loop and sanity-check them against component input /
output range expectations? You have the tools. Having
us "ghosts" speculate, is a poor substitute for that.

You might begin with breaking the loop at Vtune, sweep
Vtune manually while watching frequency and seeing
that the output which would drive Vtune, switches at
the frequency target and that the Vtune applied at that
point, is anything close to what you've got on the
'scope now. Either upper, lower bound or the average.
Click to expand...

The upper/lower limit of Vtune is around 11V/1V. In the picture, the average voltage is around the 5.9V, which is very close to the tuning voltage of that freuqency which I want to generate. So, pull out of range is less probable.

For the supply chop, I also have similar concern at first, I measured the supply pin of amplifier of loop filter, and didn't find ripple on that. I will provide more pictures on my design later, and believe we could discuss that deeper.

However, I once test the VCO using a battery, the VCO works fine. And I couldn't find any clue on VCO which leads to ringing of that line. That's all I have now.
 

Poorren, some general remarks:
At first, I understand that your loop under discussion is a PLL, right?
In this case, stability analyses in the frequency domain (ac simulations) are possible with a linearized model only.
That means: The loop is assumed to be in locked condition and the signals are regarded as PHASE information.
Thus, the VCO alone contributes already 90 deg. phase shift - leading to a PM of 90 deg.
Thus, a total PM of 85 deg for the whole loop (including loop filter) is impossible. Something is wrong (as indicated in my first reply).
 
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FvM said:
It can be measured. Operate the PLL with a slow loop filter to keep it locked, inject an AC signal in front of the VCO and observe the output of the PD.
Click to expand...

Hello FvM,
Could you do my a favor and provide more info on your method? What's the meaning of slow loop filter? Do you mean a very narrow loop filter?
And how to inject the AC signal in front of VCO? If do this, I am wondering the total loop could still keep locked. Thanks.

---------- Post added at 16:59 ---------- Previous post was at 16:50 ----------
LvW said:
Poorren, some general remarks:
At first, I understand that your loop under discussion is a PLL, right?
In this case, stability analyses in the frequency domain (ac simulations) are possible with a linearized model only.
That means: The loop is assumed to be in locked condition and the signals are regarded as PHASE information.
Thus, the VCO alone contributes already 90 deg. phase shift - leading to a PM of 90 deg.
Thus, a total PM of 85 deg for the whole loop (including loop filter) is impossible. Something is wrong (as indicated in my first reply).
Click to expand...

Hi LvW,
The loop under discussion is PLL+loop filter+VCO. I want to build a LO for a receiver IF mixer.
You are right, in ac simulation, I could ONLY find linear model for VCO and PLL. Actually, I just want to verify loop filter I designed could lead to good PM. The PM I used is the same as many books provided. It is actually the close loop phase at the frequency which the open loop gain is unity. I agree with you, there must be something wrong in real circuit which I didn't found it in simulation model.
 

poorren said:
Hi LvW,
The loop under discussion is PLL+loop filter+VCO. I want to build a LO for a receiver IF mixer.
You are right, in ac simulation, I could ONLY find linear model for VCO and PLL. Actually, I just want to verify loop filter I designed could lead to good PM. The PM I used is the same as many books provided. It is actually the close loop phase at the frequency which the open loop gain is unity. I agree with you, there must be something wrong in real circuit which I didn't found it in simulation model.
Click to expand...

Poorren, in order to avoid misunderstandings, you should try to express yourself more accurat:
* A PLL is a closed loop - including loop filter and VCO
* What kind of linear model did you "find" for the PLL?
* What means "PM I used"? You cannot "use" a phase margin; or what do you mean withPM?
*Suggestion: Post your simulation arrangement (block diagram) and we can try to give some help for solving your problem.
Regards
 

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