[SOLVED] 74HC4046 PLL with soundcard reference signal

Hello,

I designed a simple PLL frequency multiplier - phase comp II, VCO range 3-6 MHz, divider N=512, 3rd order filter, with the Fairchild 74HC4046 which has an AC input signal sensitivity of 150 mVpp according to the datasheet. The reference signal is capacitor coupled from a PC sound card (5.85-11.718 kHz).

The problem is the loop locks only for signals higher than about 2 Vrms which is the maximum output from the sound card. When it locks the loop is very stable. At lower input signal, the VCO varies between 5-6MHz even with Fref = 5 kHz, so I thought the reference signal is noisy and triggers the phase detector, and I added a simple RC LPF. I also tried using another PC, with the same result.

I apreciate any advice for making this loop lock with a reference signal under 500 mVrms and without a signal amplifier.

Thanks

The soundcard signal has ultrasonic noise (higher Nyquist spectra) and low slew-rate.
Filtering was not a big improvement, I finally added a discrete amplifier and Schmitt trigger gates on a separate board and now it works perfectly (the Schmitt trigger was absolutely needed). It seems the input sensitivity mentioned in the datasheet at 500kHz, asumes a high enough slew rate and a clean signal.