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[SOLVED] Error in using .subckt in hspice netlist

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himansg

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Hi ,

I am writing a netlist of inverter chain of two inverter using the ".subckt" function of hspice. But I am not getting the desired output. Can someone please point out the mistake ...

Code:
Inverter Chain
.lib 'tsmc035.mod' NOM

*Voltage Sources and Inputs
vdd vdd gnd 3.2
vin in gnd pat 3.2 0 0n 1p 1p 5n b010101
.global vdd

*Subcircuit Inverter
.subckt invert in out length=0.35u width=0.35u
mn1 out in gnd gnd n_mos l=length w=width
mp1 out in vdd vdd p_mos l=length w=2*width
.ends

x1 in out1 invert length=0.35u width=0.35u
x2 out1 out invert length=0.35u width=0.35u

.tran 0.1p 30n
.option post=2 nomod

.end

n_mos and p_mos are model names from the tsmc035.mod file.

Thanks.....
 

I have not used hspice netlist in a long time but I believe you need to define the gnd node as a 0 (or use a 0-voltage source between 0 and gnd).
 

hi
i think you should include your suckt in your design
use .include 'the exact path to the subckt'
for example
.include 'C:\subckt.sp'
 

I did that but it didn't work ... :(
when I simulated the circuit without using subckt I got results...

---------- Post added at 23:35 ---------- Previous post was at 23:34 ----------

I have not used hspice netlist in a long time but I believe you need to define the gnd node as a 0 (or use a 0-voltage source between 0 and gnd).

I did that but it didn't work ... :(
when I simulated the circuit without using subckt I got results...

---------- Post added at 23:37 ---------- Previous post was at 23:35 ----------

hi
i think you should include your suckt in your design
use .include 'the exact path to the subckt'
for example
.include 'C:\subckt.sp'

That is another method to write the same code ..... This doesn't change anything ... Problem is anywhere else.....
 

Hi
Try to define .global vdd gnd
 

I got the mistake .... the correction is :

Code:
mp1 out in vdd vdd p_mos l=length w='2*width'

thanks for help.....
 

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