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About TDL and Verilog HDL

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anirbanphys

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What is TDL and how this is associated with Verilog HDL?
 

Hi buddy,

where did you come across this? As far as my search goes TDL is a task description language which is used for controlling robots and space crafts and it is a extension of CPP and Verilog as we all know is a HDL.
Maybe they are not associated!!
 

As the thread indicates it(TDL) is a format which we get as output from a tool....similar to .ddc from synopsys tools....

So TDL is a format(used in ATPG tools) and Verilog is a HDL..I still cant find any relation between these two
 

Verilog HDL is used in designing the digital circuit.
TDL is stimulus provided for Silicon which is being tested on a tester.

Hope it clarifies!!
 

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