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How to choose the best nf (number of fingers) for lowest mismatch?

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dtzounakos

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For example let's say that we have a current mirror. How do i know what is the
best choice of nf for both transistors? I am asking this because i have
noticed through monte carlo analysis that keeping the ratio of Wtotal (so the
current ratio also constant!) constant and change only the nf, the mismatch of ΔID/ID is being changed!Also i have noticed that decreasing nf mismatch sometimes increases and sometimes decreases! Why this happen as the operation region and point is constant and same?

Thanks!
 

See if your foundry has graphs that show mismatch vs
W for fixed L or for constant area, as well as MM vs A.
There are edge effects which are distinct from plain
gate area effects. If you can find such data, stay away
from (wider than) the inflection point.

But I've seen schemes where W is Wtotal and fingers
are the divisor, and I've seen ones where W is the
literal drawn width and fingers is the multiplier. So
you need to know that, to know if fingers "should"
help or hurt.

If fingers is changing device total width and area
you may be seeing non-matching, but match-affecting
effects such as moving closer or further from saturation.
 

dick_freebird said:
But I've seen schemes where W is Wtotal and fingers
are the divisor, and I've seen ones where W is the
literal drawn width and fingers is the multiplier. So
you need to know that, to know if fingers "should"
help or hurt.

If fingers is changing device total width and area
you may be seeing non-matching, but match-affecting
effects such as moving closer or further from saturation.
Click to expand...

To be more accurately, when i say i change nf (up or down) in mosfet properties (Q button), i keep constant the total Width and change only the Wfinger (the width of each interdigitated mosfet)
So you tell me that in my foundry manual there are graphs that show me mismatch relationship with fingers?
 

I doun't know what your foundry provides, but my technology
group breaks down mismatch data into A, and iso-area L and W
charts. You can ask.
 

On one hand, mismatch is improved if gate area is increased. On the other hand, mismatch is improved if we split the transistor due to the statistics of larger numbers have a greater chance to achieve something closer to the mean. There is no fixed rule to say which is better except well characterized silicon. Furthermore, whatever simulations you do probably do not take into account the layout of the transistors.

What I usually do for critical transistor pairs is to select a multiplier which gives me the most squarish layout. The other techniques like using large overdrive for current mirrors and increasing L gives a more guaranteed method to improve mismatch.
 
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