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Xilinx ISE Source Path

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priestnot

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Hello...

I am trying to build a fpga configurator in java. It will create the verilog files based on a text file created by the user witch tells the software witch modules to use. So the user just need to synthesize the toplevel in the ISE.

I wold like to know if some one knows were the ISE project folder the ISE stores the paths to the verilog sources of the project so i can edit them outside ISE...

I tried the projectffolder/toplevel.prj (and it is changed when ISE opens the project)
I also tried the projectffolder/FPGA_Core_xdb/tmp/ise/__REGISTRY__/ProjectSeedData/UserSourceFiles/regkeys (and it is also changed when ISE opens the project)

I realy hope that is not on the .ise binary file...
 

There is a .xise file with the same name as the .ise (project file).
If you open it you can see the paths

Code: 
<files>
    <file xil_pn:name="[B]test2.vhd[/B]" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="[B]New Folder/test3.vhd[/B]" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
  </files>

Alex
 

I could not find any .xise file in the ISE project folder...
I am using ISE 10.3...
 

I'm using ISE 11.4.

create a test project, zip the project folder and post it here so i can search the content.

Alex
 

user_logic.prj includes the paths to the .v sources, i don't know if it is created from ISE because .ise has a different name.

Alex
 

Ye si know that but if i change the user_logic.prj to point to the new sources and then open ISE it will overwrite it and put it back as it was.
 

I thought you were searching for the source paths.
So you want to change the files which are included in the project, i assume that this info is stored in the .ise file,
there isn't any other file that includes the source names.
If you open .ise in a txt editor and do a search for specific source names you will find them but i still don't know if you can change them

Alex
 

The .ise file is not a text file its binnary i cannot open it with a text editor.

But thanks any way. I will add the modules to the top level verilog source code. Its not a great solution but it will work...

Thanks again...
 

You can open it if you rename it to text or use any editor and select open and choose the .ise file.
in included many unregognisable characters but in the end of the file there is a big test part, it uses a ppecific pattern, see if you can use it.

|File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/user_logic.cmd_log|PLUGIN_General|1295013899| FILE_CMD_LOG |Generic||user_logic.cmd_log user_logic.cmd_log DESUT_CMD_LOG |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/xst|PLUGIN_General|1294420568| FILE_DIRECTORY |Generic||xst xst DESUT_DIRECTORY |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/user_logic.ngr|PLUGIN_NGR|1295013915| PLUGIN_NGR FILE_NGR |Module||user_logic user_logic DESUT_NGR 4vfx12sf363-12 |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/user_logic.ngc|PLUGIN_NGC|1294943857| PLUGIN_NGC FILE_NGC DESUT_NGC xc4vfx12-12-sf363 |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/user_logic.prj|PLUGIN_General|1295013899| FILE_XST_PROJECT |Generic||user_logic.prj user_logic.prj DESUT_XST_PROJECT |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/user_logic.syr|PLUGIN_General|1295013919| FILE_XST_REPORT |Generic||user_logic.syr user_logic.syr DESUT_XST_REPORT |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/user_logic.lso|PLUGIN_General|1294420568| FILE_LSO |Generic||user_logic.lso user_logic.lso DESUT_LSO |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/user_logic.xst|PLUGIN_General|1295013899| FILE_XST |Generic||user_logic.xst user_logic.xst DESUT_XST |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/src/user_logic.v|PLUGIN_Verilog|1290508053| |ComponentInstantiation||user_logic|user_logic|core1|core| |ComponentInstantiation||user_logic|user_logic|dpram1|DPRAM| core1 core dpram1 DPRAM |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/src/servoctrl.v|PLUGIN_Verilog|1279293609| |Module||servoctrl servoctrl |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/src/sample_data.v|PLUGIN_Verilog|1288716056| |Module||sample_data

Alex

---------- Post added at 17:19 ---------- Previous post was at 17:16 ----------

I like to use programmers notepad (windows), Programmer's Notepad
opens big files very fast and has many enhancements and Syntax Highlighting for lots of languages.
You will also be ablt to see special characters that normal text editors cant show (like null)

Alex
 

Autch...
I tried to open it with gedit (linux ubuntu) and it could not open it...
And the result that you display its nor easy to read and not easy to manipulate...
As you said:
included many unrecognizable characters
Click to expand...

But i suppose its easy to do as i said and copy the modules sources to the verilog file of the toplevel...

Once again thanks for the help...
 

The part above was using windows notepad,
try to open it using open office writer, or leaf or Kwrite or any other editor you may have.
Yes it is complicated but i see a specific pattern

|Module||motiondetector_tb motiondetector_tb md |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/src/MAGSwitch.v|PLUGIN_Verilog|1288357399|

|Module||MAGSwitch MAGSwitch |File||/media/MooreD/edu/workspace/FPGA/Suzaku/RL_Proj_Suzaku_apagar1/ISE_sz410/src/MAGSwitch_tb.v|PLUGIN_Verilog|1279124897|

Alex
 
Last edited:

Ill give it a try... i will post some results ...
 

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